Register-mapped programmable timer in SystemVerilog: set load and reload values, start it, and receive an interrupt request on every overflow. Supports start, stop, enable, disable and interrupt masking. Simulated with Verilator and GTKWave, synthesizable with Yosys.
asic fpga timer verilog systemverilog hardware-designs interrupts gtkwave vlsi yosys digital-design verilator rtl-design interrupt-controller register-map programmable-timer
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Updated
Nov 3, 2026