FLASHICON
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parameterized-8-bit-alu
parameterized-8-bit-alu PublicSynthesis-ready parameterized 8-bit ALU in SystemVerilog with 10 arithmetic, logic, shift and comparison operations. Verified with Verilator and GTKWave, synthesized with Yosys.
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programmable-timer-and-interrupt-controller
programmable-timer-and-interrupt-controller PublicRegister-mapped programmable timer in SystemVerilog: set load and reload values, start it, and receive an interrupt request on every overflow. Supports start, stop, enable, disable and interrupt ma…
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uart-tx-rx-communication-ip
uart-tx-rx-communication-ip PublicUART core in SystemVerilog with a transmitter, receiver and baud rate generator. Frames each byte with start, data, parity and stop bits, flags errors on reception and buffers data through FIFOs. C…
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synchronous-fifo-ip
synchronous-fifo-ip PublicParameterized synchronous FIFO in SystemVerilog built on a circular memory buffer. Read and write pointers drive full, empty, almost-full and almost-empty flags, and assertions guard against overfl…
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asynchronous-fifo-cdc-subsystem
asynchronous-fifo-cdc-subsystem PublicDual-clock FIFO with a clock domain crossing subsystem, written in SystemVerilog. Gray code pointers pass through two-stage synchronizers, so the write and read sides run on unrelated clocks withou…
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multi-port-ram-register-file
multi-port-ram-register-file PublicRegister file with one synchronous write port and several independent read ports, modeled in SystemVerilog like a small SRAM. Each read port decodes its own address, so multiple reads and a write c…
Repositories
- industry-style-digital-asic-subsystem-rtl-to-gdsii Public
Digital ASIC subsystem that integrates UART, FIFO, GPIO, timer and register file IP behind an AXI interconnect, then carries it through system-level verification, synthesis, timing analysis and physical design to GDSII.
- risc-v-mini-soc-end-to-end-asic-implementation Public
A full digital ASIC flow on a RISC-V mini-SoC. SystemVerilog RTL, UVM verification, synthesis, timing analysis, floorplanning, placement, CTS, routing, DRC and LVS checks, ending in a GDSII layout.
- risc-v-rtl-to-gdsii-physical-design Public
Physical design of a RISC-V SoC from gate-level netlist to GDSII: floorplan, power grid, pin placement, cell placement, clock tree, global and detailed routing, then DRC and LVS checks, using OpenLane and OpenROAD.
- risc-v-static-timing-analysis-ppa-optimization Public
Static timing analysis and PPA tuning for a synthesized RISC-V netlist. Applies SDC constraints, checks setup and hold slack, finds the critical path, then recovers timing through logic restructuring and cell swapping, comparing area and power before and after.
- risc-v-rtl-to-gates-synthesis-netlist Public
Constraint-driven synthesis flow that turns a RISC-V SoC written in SystemVerilog into a technology-mapped gate-level netlist, with timing, area and power reports and a PPA review, built on open-source tools.
- risc-v-soc-cpu-sram-amba-peripherals Public
RISC-V system-on-chip in SystemVerilog that connects a pipelined RV32I CPU, SRAM and UART, GPIO and timer peripherals through an AXI4 interconnect with address decoding and a memory-mapped register map.
- 5-stage-pipelined-rv32i-risc-v-processor Public
Five-stage pipelined RV32I RISC-V processor in SystemVerilog with pipeline registers, hazard detection unit, data forwarding and branch handling, built for higher instruction throughput.
- rv32i-single-cycle-risc-v-processor Public
Synthesizable RV32I RISC-V core in SystemVerilog where fetch, decode, execute, memory access and write-back complete in a single clock cycle, with ALU, register file, immediate generator and control unit.
- constrained-random-fifo-cdc-verification Public
Coverage-driven verification of an asynchronous FIFO across independent write and read clocks, using constrained-random stimulus, a reference scoreboard, CDC checks, assertions and cross coverage in SystemVerilog.
- uvm-based-amba-ip-verification-environment Public
A reusable UVM testbench for AMBA IP, with constrained transaction generation, a protocol driver and monitor, a reference scoreboard, assertions and functional coverage, written in SystemVerilog.
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