logic-simulation

Standalone (offline) version of the Circuit Simulator with small modifications based on modified NW.js.

Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments, allowing host compiled programs to run in a logic simulation. and drive a memory mapped bus

A platform for learning and experimenting with logic circuits

Collected article documents in PDF covering subject with co-simulation, embedded systems, software development and logic design and verification

A simple digital logic simulator written as a learning exercise in C++

Full-timing gate-level logic simulator encoded entirely in C++ templates

Logicarium is a minimalist, performant, visual logic design environment. Design complex digital systems using a high-density, performant interface. Custom gates for modular logic, and a visual DSL for script with real-time synchronization and code generation, all hardware-accelerated.

Create simulated logic circuits with this online logic simulator

Windows application for designing and simulating digital logic circuits, written in C++ using CMU graphics library.

An ugly & interactive logic gate visualizer written in Java using plain old Java Swing

VHDL implementations, ALU designs, simulation testbenches, and logic processor coursework for ČVUT FEL BE5B35LSP.

successor to my other logic simulator PygameLogicSim. This project separates the simulator into a front end and a back end

RiscV Environment for Simulation (R4VES) is a generic and modular framework that eases the grunt work required in order to perform pre/post-synthesis logic and fault simulation on RISC-V cores based on Model/QuestaSim and Z01X.

Python-based VLSI Fault Simulator for ISCAS-85 benchmarks. Features a CLI engine for Stuck-at Fault injection, Logic Simulation, and reduced fault lists via Equivalence & Dominance collapsing algorithms.

A simple digital logic simulator

FlowEngine.HR is a high-performance visual architect and logic execution engine designed for HR process automation. Built with React and TypeScript, it features real-time REST API simulation, advanced graph validation, and a custom Midnight Graphite design system for professional-grade workflow modeling.

Digital logic simulator that supports ternary circuit design. Simulator is event-driven with zero delay and iterates delta cycles until quiescence.

Gate-level logic simulator and static timing analyzer for iverilog VVP netlists, with bit-parallel simulation and an ESPRESSO round trip

Event-driven gate-level logic simulator in C++