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[SYCL] PR 3 - Remove FPGA attributes from SYCL FE #21735
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
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@@ -2915,73 +2915,6 @@ def Mode : Attr { | |
| let PragmaAttributeSupport = 0; | ||
| } | ||
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| def SYCLIntelIVDep : StmtAttr { | ||
| let Spellings = [CXX11<"intel", "ivdep">]; | ||
| let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt], | ||
| ErrorDiag, "'for', 'while', and 'do' statements">; | ||
| let Args = [ | ||
| ExprArgument<"SafelenExpr", /*opt*/1>, ExprArgument<"ArrayExpr", /*opt*/1>, | ||
| UnsignedArgument<"SafelenValue", /*opt*/1> | ||
| ]; | ||
| let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost]; | ||
| let AdditionalMembers = [{ | ||
| bool isDependent() const { | ||
| return (getSafelenExpr() && | ||
| getSafelenExpr()->isInstantiationDependent()) || | ||
| (getArrayExpr() && getArrayExpr()->isInstantiationDependent()); | ||
| } | ||
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| const ValueDecl *getArrayDecl() const { | ||
| const Expr* E = getArrayExpr(); | ||
| if (!E) return nullptr; | ||
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| if (const auto *DRE = dyn_cast<DeclRefExpr>(E)) | ||
| return cast<ValueDecl>(DRE->getDecl()->getCanonicalDecl()); | ||
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| return cast<ValueDecl>( | ||
| cast<MemberExpr>(E)->getMemberDecl()->getCanonicalDecl()); | ||
| } | ||
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| bool isInf() const { | ||
| return !getSafelenExpr(); | ||
| } | ||
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| static bool SafelenCompare(const SYCLIntelIVDepAttr *LHS, | ||
| const SYCLIntelIVDepAttr *RHS) { | ||
| // INF < INF is false, !INF < INF is true. | ||
| if (!RHS->getSafelenExpr()) | ||
| return false; | ||
| if (!LHS->getSafelenExpr()) | ||
| return true; | ||
| return LHS->getSafelenValue() > RHS->getSafelenValue(); | ||
| } | ||
| }]; | ||
| let Documentation = [SYCLIntelIVDepAttrDocs]; | ||
|
Contributor
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. Wait, should we also remove all the docs?
Contributor
Author
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. Thanks, I removed from AttrDocs.td. I will go back and see if I missed removing any from the previous two PRs; and if it is from the merged one, will create a new PR for that. |
||
| } | ||
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| def SYCLIntelInitiationInterval : DeclOrStmtAttr { | ||
| let Spellings = [CXX11<"intel", "ii">, | ||
| CXX11<"intel", "initiation_interval">]; | ||
| let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt, Function], | ||
| ErrorDiag, | ||
| "'for', 'while', 'do' statements, and functions">; | ||
| let Args = [ExprArgument<"NExpr">]; | ||
| let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost]; | ||
| let Documentation = [SYCLIntelInitiationIntervalAttrDocs]; | ||
| let SupportsNonconformingLambdaSyntax = 1; | ||
| } | ||
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| def SYCLIntelMaxConcurrency : DeclOrStmtAttr { | ||
| let Spellings = [CXX11<"intel", "max_concurrency">]; | ||
| let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt, Function], | ||
| ErrorDiag, | ||
| "'for', 'while', 'do' statements, and functions">; | ||
| let Args = [ExprArgument<"NExpr">]; | ||
| let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost]; | ||
| let Documentation = [SYCLIntelMaxConcurrencyAttrDocs]; | ||
| let SupportsNonconformingLambdaSyntax = 1; | ||
| } | ||
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| def SYCLIntelLoopCoalesce : StmtAttr { | ||
| let Spellings = [CXX11<"intel", "loop_coalesce">]; | ||
| let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt], | ||
|
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@@ -2991,26 +2924,6 @@ def SYCLIntelLoopCoalesce : StmtAttr { | |
| let Documentation = [SYCLIntelLoopCoalesceAttrDocs]; | ||
| } | ||
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| def SYCLIntelDisableLoopPipelining : DeclOrStmtAttr { | ||
| let Spellings = [CXX11<"intel", "disable_loop_pipelining">]; | ||
| let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt, Function], | ||
| ErrorDiag, | ||
| "'for', 'while', 'do' statements, and functions">; | ||
| let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost]; | ||
| let Documentation = [SYCLIntelDisableLoopPipeliningAttrDocs]; | ||
| let SupportsNonconformingLambdaSyntax = 1; | ||
| let SimpleHandler = 1; | ||
| } | ||
| def : MutualExclusions<[SYCLIntelInitiationInterval, | ||
| SYCLIntelDisableLoopPipelining]>; | ||
| def : MutualExclusions<[SYCLIntelIVDep, | ||
| SYCLIntelDisableLoopPipelining]>; | ||
| def : MutualExclusions<[SYCLIntelMaxConcurrency, | ||
| SYCLIntelDisableLoopPipelining]>; | ||
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| def : MutualExclusions<[SYCLIntelMaxConcurrency, | ||
| SYCLIntelDisableLoopPipelining]>; | ||
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| def SYCLIntelMaxInterleaving : StmtAttr { | ||
| let Spellings = [CXX11<"intel", "max_interleaving">]; | ||
| let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt], | ||
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@@ -3020,39 +2933,6 @@ def SYCLIntelMaxInterleaving : StmtAttr { | |
| let Documentation = [SYCLIntelMaxInterleavingAttrDocs]; | ||
| } | ||
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| def SYCLIntelSpeculatedIterations : StmtAttr { | ||
| let Spellings = [CXX11<"intel", "speculated_iterations">]; | ||
| let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt], | ||
| ErrorDiag, "'for', 'while', and 'do' statements">; | ||
| let Args = [ExprArgument<"NExpr">]; | ||
| let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost]; | ||
| let Documentation = [SYCLIntelSpeculatedIterationsAttrDocs]; | ||
| } | ||
| def : MutualExclusions<[SYCLIntelDisableLoopPipelining, | ||
| SYCLIntelSpeculatedIterations]>; | ||
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| def SYCLIntelMaxReinvocationDelay : StmtAttr { | ||
| let Spellings = [CXX11<"intel", "max_reinvocation_delay">]; | ||
| let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt], | ||
| ErrorDiag, "'for', 'while', and 'do' statements">; | ||
| let Args = [ExprArgument<"NExpr">]; | ||
| let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost]; | ||
| let Documentation = [SYCLIntelMaxReinvocationDelayAttrDocs]; | ||
| } | ||
| def : MutualExclusions<[SYCLIntelDisableLoopPipelining, | ||
| SYCLIntelMaxReinvocationDelay]>; | ||
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| def SYCLIntelEnableLoopPipelining : StmtAttr { | ||
| let Spellings = [CXX11<"intel", "enable_loop_pipelining">]; | ||
| let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt], | ||
| ErrorDiag, "'for', 'while', and 'do' statements">; | ||
| let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost]; | ||
| let Documentation = [SYCLIntelEnableLoopPipeliningAttrDocs]; | ||
| } | ||
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| def : MutualExclusions<[SYCLIntelDisableLoopPipelining, | ||
| SYCLIntelEnableLoopPipelining]>; | ||
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| def SYCLIntelDoublePump : Attr { | ||
| let Spellings = [CXX11<"intel", "doublepump">]; | ||
| let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost]; | ||
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I was curious about what ivdep is and google gave me this https://www.intel.com/content/www/us/en/docs/oneapi-fpga-add-on/developer-guide/2025-0/ivdep-attribute.html . I wonder if need to ask someone to remove this from somewhere too