[SYCL] PR 3 - Remove FPGA attributes from SYCL FE#21735
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premanandrao wants to merge 3 commits intointel:syclfrom
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[SYCL] PR 3 - Remove FPGA attributes from SYCL FE#21735premanandrao wants to merge 3 commits intointel:syclfrom
premanandrao wants to merge 3 commits intointel:syclfrom
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This removes the following attributes: [[intel::ivdep]] [[intel::initiation_interval]] [[intel::ii]] [[intel::max_concurrency]] [[intel::speculated_iterations]] [[intel::max_reinvocation_delay]] [[intel::disable_loop_pipelining]] [[intel::enable_loop_pipelining]]
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Fznamznon
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Apr 13, 2026
| let PragmaAttributeSupport = 0; | ||
| } | ||
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| def SYCLIntelIVDep : StmtAttr { |
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I was curious about what ivdep is and google gave me this https://www.intel.com/content/www/us/en/docs/oneapi-fpga-add-on/developer-guide/2025-0/ivdep-attribute.html . I wonder if need to ask someone to remove this from somewhere too
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| return LHS->getSafelenValue() > RHS->getSafelenValue(); | ||
| } | ||
| }]; | ||
| let Documentation = [SYCLIntelIVDepAttrDocs]; |
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Wait, should we also remove all the docs?
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Requesting changes so we don't miss docs removal
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This removes the following attributes:
[[intel::ivdep]]
[[intel::initiation_interval]]
[[intel::ii]]
[[intel::max_concurrency]]
[[intel::speculated_iterations]]
[[intel::max_reinvocation_delay]]
[[intel::disable_loop_pipelining]]
[[intel::enable_loop_pipelining]]