Pinned Loading

1. tinytapeout-uart tinytapeout-uart Public

   A FIFO-buffered UART with an APB register block, verified with self-checking testbenches and taped out on the Tiny Tapeout TTSKY26c shuttle.

   Python

2. rv32i-single-cycle rv32i-single-cycle Public

   A 32-bit single-cycle RISC-V CPU core implementing the RV32I base instruction set, verified by lockstep co-simulation against the Spike reference model.

   SystemVerilog

3. uart uart Public

   A UART transceiver with a 16x-oversampling receiver, self-checking testbenches, formally verified RX/TX, and Basys 3 FPGA loopback validation.

   SystemVerilog

4. fifo fifo Public

   A configurable synchronous and asynchronous FIFO with Gray-code clock-domain crossing, verified with self-checking testbenches and an unbounded SymbiYosys formal proof.

   SystemVerilog

5. self-checking-testbenches self-checking-testbenches Public

   Small RTL modules, each checked against a reference model every clock, with formal proof, lint, CI, and Basys 3 FPGA validation.

   SystemVerilog