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atomic: hwspinlock backend for cxd56, rp2040, lc823450 - #19868

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atomic: hwspinlock backend for cxd56, rp2040, lc823450#19868
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@zhangyu-duck zhangyu-duck commented Aug 16, 2026 •
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Summary

Add hwspinlock-based atomic backend for multi-core capable chips:

  • Add hwspinlock driver implementations for cxd56, rp2040, and lc823450
  • Implement atomic operations using hwspinlock when LIBC_ATOMIC_HWSPINLOCK is selected
  • Rename arch_atomic_irq.c back to arch_atomic.c with combined IRQ + hwspinlock implementation

This PR depends on #19867 (multi-backend framework + builtin + API rename).

Stacked PR chain

Depends on #19867. This is PR 3 of 3:

Test

CI testbuild across ARM/RISC-V/SIM targets.

@github-actions github-actions Bot added Area: Bluetooth Arch: arm Issues related to ARM (32-bit) architecture Arch: arm64 Issues related to ARM64 (64-bit) architecture Arch: avr Issues related to all AVR(8-bit or 32-bit) architectures Arch: risc-v Issues related to the RISC-V (32-bit or 64-bit) architecture Arch: simulator Issues related to the SIMulator Arch: sparc Issues related to the SPARC architecture Arch: xtensa Issues related to the Xtensa architecture Size: XL The size of the change in this PR is very large. Consider breaking down the PR into smaller pieces. labels Aug 16, 2026
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MemBrowse Memory Report

arduino-mega2560

  • flash: .text +50 B (+0.1%, 67,592 B / 262,144 B, total: 26% used)

mirtoo

  • kseg0_progmem: .text -668 B (-1.0%, 66,808 B / 131,072 B, total: 51% used)

rx65n-rsk2mb

  • ROM: .text +80 B (+0.1%, 87,408 B / 2,097,152 B, total: 4% used)

s698pm-dkit

@github-actions github-actions Bot added the Arch: renesas Issues related to the Renesas chips label Aug 17, 2026
@zhangyu-duck zhangyu-duck mentioned this pull request Aug 18, 2026
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@zhangyu-duck zhangyu-duck reopened this Aug 18, 2026
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🔗 Cross-repo PR dependencies

The read-only Build run reported the following dependent PR(s) and fetched head SHA(s):

CI run: https://github.com/apache/nuttx/actions/runs/32090737453

@zhangyu-duck
zhangyu-duck force-pushed the pr3-atomic-builtin branch 3 times, most recently from f0c81bb to 8b63c5f Compare August 18, 2026 08:22
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🔗 Cross-repo PR dependencies

The read-only Build run reported the following dependent PR(s) and fetched head SHA(s):

CI run: https://github.com/apache/nuttx/actions/runs/32116047543

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🔗 Cross-repo PR dependencies

The read-only Build run reported the following dependent PR(s) and fetched head SHA(s):

CI run: https://github.com/apache/nuttx/actions/runs/32132885300

@xiaoxiang781216 xiaoxiang781216 mentioned this pull request Aug 19, 2026
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@zhangyu-duck zhangyu-duck changed the title atomic: use toolchain builtin and rename atomic_fetch_xxx to atomic_xxx atomic: hwspinlock backend for cxd56, rp2040, lc823450 Aug 19, 2026
@zhangyu-duck zhangyu-duck mentioned this pull request Aug 19, 2026
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zhangyu-duck marked this pull request as ready for review August 19, 2026 06:35
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zhangyu-duck requested a review from jerpelea as a code owner August 19, 2026 06:35
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zhangyu-duck marked this pull request as draft August 19, 2026 07:29
@jerpelea

jerpelea commented Aug 19, 2026

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please split the PR in separate PRs
EX:

  1. driver and documentation
  2. ARM arch implementation and documentation

@zhangyuduck
nuttx/libc: arch_atomic.c uses IRQ switching, no SMP support
c14be62 
The atomic implementation of machine/arch_atomic.c is achieved by
switching interrupts. This version does not support SMP.

Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
@zhangyuduck
arch/tricore: add arch atomic function
f00fd9f 
Tricore gcc does not support atomic interface but some users need to
use atomic operations, so support atomic function using tricore arch
instructions (__cmpAndSwap/__swap/__ld32).

Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
@zhangyuduck
nuttx/libc: refine the atomic related Kconfig
9b89a55 
Refine the atomic Kconfig to support multiple backends:
LIBC_ATOMIC_TOOLCHAIN (compiler builtins), LIBC_ATOMIC_ARCH (arch
instructions), and LIBC_ATOMIC_IRQ (interrupt disable). Rename
arch_atomic.c to arch_atomic_irq.c since it supports the IRQ backend.

Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
@zhangyuduck
nuttx/atomic: select LIBC_ATOMIC_IRQ for archs without atomic support
5081793 
Select LIBC_ATOMIC_IRQ at the architecture level (ARM7TDMI, ARM926EJS,
ARMv6M) for chips that do not support atomic operations natively. This
covers all ARM7TDMI, ARM926EJS, and Cortex-M0 based chips automatically.

Also select LIBC_ATOMIC_IRQ for specific non-ARM architectures (AVR,
RISC-V, SPARC, Xtensa) that lack atomic instruction support.

Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
@zhangyuduck
nuttx: use unified interface in <nuttx/atomic.h>
6b6e73f 
Replace atomic_load with atomic_read in call sites to use the
unified interface defined in <nuttx/atomic.h>.

Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
@zhangyuduck
nuttx/atomic: for builtin atomic, a wrapper is used to unify the names.
cce88e6 
1. for tasking, map __c11_atomic_xxx as tasking_atomic_xxx
2. for msvc, map  _Interlocked_xxx as msvc_atomic_xxx
3. if no special map, use gcc/clang as default as they are most widely used.

Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
@zhangyuduck
nuttx/atomic: use toolchain builtin atomic function
6d7ed56 
The reason for using builtin atomic is that in C++, when include <atomic> in <nuttx/atomic.h> easily conflicts with third-party function libraries. We wanted to completely separate the implementation of <nuttx/atomic.h>.

There are two points:
1. use builtin function directly.
2. Without the standard library implementation, need implement "atomic_fetch_xxx", leading conflicts with the standard library used by third-party programs, introducing redefinition issues and requiring name changes.

Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
@zhangyuduck
nuttx/atomic: replace atomic_fetch_xxx with atomic_xxx just like zephyr
ff8d203 
Rename atomic_fetch_add/sub/or/and/xor to atomic_add/sub/or/and/xor
to avoid conflicts with the C/C++ standard library naming. The
atomic_fetch_xxx naming is reserved by the standard; keeping it causes
function name conflicts when source files indirectly include both
<nuttx/atomic.h> and <atomic>/<stdatomic.h>.

Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
@zhangyuduck
nuttx/atomic.h: use _Atomic define atomic_t.
110b0b1 
1. use _atomic as wrapper because if _Atomic empty, may affects the compilation of other files:

2. for clang builtin function, it donot accept param with keyword "_Atomic"

Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
@zhangyuduck
nuttx/hwspinlock: hwspinlock should based on irq instead of spinlock_irq
79c96c5 
Use irq-based critical sections instead of spinlock_irq to avoid
potential deadlock in atomic contexts.

Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
@zhangyuduck
arch/arm/src: add hwspinlock driver for cxd56, rp2040 and lc823450
6cec022 
Add hardware spinlock driver implementations for cxd56, rp2040, and
lc823450 chips. These drivers provide the hwspinlock_ops_s interface
used by the atomic hwspinlock backend.

Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
@zhangyuduck
libc/machine: realize atomic based on hwspinlock
05ff423 
Implement atomic_lock/atomic_unlock using hwspinlock when
CONFIG_LIBC_ATOMIC_HWSPINLOCK is selected, and using up_irq_save/
up_irq_restore when CONFIG_LIBC_ATOMIC_IRQ is selected. Rename
arch_atomic_irq.c to arch_atomic.c.

The 64-bit atomic operations use spinlock (spin_lock_irqsave)
regardless of the selected backend, ensuring multi-core safety.

Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
@zhangyuduck
arch/arm/src: realize atomic for cxd56, rp2040 and lc823450
19b927c 
Add per-chip atomic hwspinlock device definitions for cxd56, rp2040,
and lc823450. These provide the hardware spinlock device used by the
atomic hwspinlock backend for multi-core atomic operations.

Replace CXD56_TESTSET/CXD56_TESTSET_WITH_HWSEM with
CXD56_ATOMIC_WITH_HWSEM which selects LIBC_ATOMIC_HWSPINLOCK,
bridging the old chip-specific testset mechanism to the new generic
atomic backend framework.

Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
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Arch: arm Issues related to ARM (32-bit) architecture Arch: arm64 Issues related to ARM64 (64-bit) architecture Arch: avr Issues related to all AVR(8-bit or 32-bit) architectures Arch: renesas Issues related to the Renesas chips Arch: risc-v Issues related to the RISC-V (32-bit or 64-bit) architecture Arch: simulator Issues related to the SIMulator Arch: sparc Issues related to the SPARC architecture Arch: xtensa Issues related to the Xtensa architecture Area: Bluetooth Board: arm Size: XL The size of the change in this PR is very large. Consider breaking down the PR into smaller pieces.

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