[RegAllocFast] Consume SSA MachineIR, absorbing PHI and two-address lowering

llvm/docs/ReleaseNotes.md

@@ -131,6 +131,12 @@ Makes programs 10x faster by doing Special New Thing.
 
 ### Changes to the CodeGen infrastructure
 
+* The fast register allocator can consume SSA machine IR, lowering PHI nodes and
+  tied operands itself. X86 and AArch64 enable this, so at `-O0` their pipelines
+  no longer run `PHIElimination` and `TwoAddressInstructionPass`. Command lines
+  that name either pass in `-start-before`, `-start-after`, `-stop-before`,
+  `-stop-after` or `-run-pass` need `-regalloc-fast-ssa=0`, which restores them.
+
 ### Changes to the Metadata Info
 
 ### Changes to the Debug Info

llvm/include/llvm/CodeGen/RegAllocFast.h

@@ -27,20 +27,13 @@ class RegAllocFastPass : public RequiredPassInfoMixin<RegAllocFastPass> {
 
   RegAllocFastPass(Options Opts = Options()) : Opts(std::move(Opts)) {}
 
-  MachineFunctionProperties getRequiredProperties() const {
-    return MachineFunctionProperties().setNoPHIs();
-  }
-
   MachineFunctionProperties getSetProperties() const {
-    if (Opts.ClearVRegs) {
-      return MachineFunctionProperties().setNoVRegs();
-    }
-
-    return MachineFunctionProperties();
-  }
-
-  MachineFunctionProperties getClearedProperties() const {
-    return MachineFunctionProperties().setIsSSA();
+    MachineFunctionProperties P;
+    P.setNoPHIs();
+    P.setTiedOpsRewritten();
+    if (Opts.ClearVRegs)
+      P.setNoVRegs();
+    return P;
   }
 
   LLVM_ABI PreservedAnalyses run(MachineFunction &MF,

llvm/include/llvm/CodeGen/TargetPassConfig.h

@@ -478,6 +478,11 @@ class LLVM_ABI TargetPassConfig : public ImmutablePass {
 LLVM_ABI void registerCodeGenCallback(PassInstrumentationCallbacks &PIC,
                                       TargetMachine &);
 
+/// Whether the fast register allocator consumes SSA MachineIR for \p TM,
+/// resolving the target default against -regalloc-fast-ssa. Shared by both
+/// codegen pipelines.
+LLVM_ABI bool useSSAFastRegAlloc(const TargetMachine &TM);
+
 } // end namespace llvm
 
 #endif // LLVM_CODEGEN_TARGETPASSCONFIG_H

llvm/include/llvm/Passes/CodeGenPassBuilder.h

@@ -1221,8 +1221,12 @@ CodeGenPassBuilder<Derived, TargetMachineT>::addRegAssignAndRewriteOptimized(
 template <typename Derived, typename TargetMachineT>
 Error CodeGenPassBuilder<Derived, TargetMachineT>::addFastRegAlloc(
     PassManagerWrapper &PMW) const {
-  addMachineFunctionPass(PHIEliminationPass(), PMW);
-  addMachineFunctionPass(TwoAddressInstructionPass(), PMW);
+  // When the fast allocator consumes SSA MachineIR it lowers PHIs and tied
+  // operands itself, detecting the input form per function from IsSSA.
+  if (!useSSAFastRegAlloc(TM)) {
+    addMachineFunctionPass(PHIEliminationPass(), PMW);
+    addMachineFunctionPass(TwoAddressInstructionPass(), PMW);
+  }
   return derived().addRegAssignAndRewriteFast(PMW);
 }
 

llvm/include/llvm/Target/TargetMachine.h

@@ -120,6 +120,7 @@ class LLVM_ABI TargetMachine {
 
   unsigned RequireStructuredCFG : 1;
   unsigned O0WantsFastISel : 1;
+  unsigned EnableSSAFastRegAlloc : 1;
 
   // PGO related tunables.
   std::optional<PGOOptions> PGOOption;
@@ -260,6 +261,14 @@ class LLVM_ABI TargetMachine {
   bool requiresStructuredCFG() const { return RequireStructuredCFG; }
   void setRequiresStructuredCFG(bool Value) { RequireStructuredCFG = Value; }
 
+  /// Whether the fast register allocator consumes SSA MachineIR, lowering
+  /// PHIs and tied operands itself instead of running PHIElimination and
+  /// TwoAddressInstructionPass.
+  /// TODO: AMDGPU inserts passes anchored on those pass IDs, must leave this
+  /// false.
+  bool enableSSAFastRegAlloc() const { return EnableSSAFastRegAlloc; }
+  void setEnableSSAFastRegAlloc(bool Value) { EnableSSAFastRegAlloc = Value; }
+
   /// Returns the code generation relocation model. The choices are static, PIC,
   /// and dynamic-no-pic, and target default.
   Reloc::Model getRelocationModel() const;