[RegAllocFast] Consume SSA MachineIR, absorbing PHI and two-address lowering

[MaskRay]

PHIElimination and TwoAddressInstructionPass cost 3.8-4.1% of llc -O0 time in whole-function rewrite walks, and the allocator then cleans up after their output. Teach RegAllocFast to consume SSA MachineIR, skipping both passes:

• PHI sources and destinations are cross-block values, so they already live in dedicated stack slots. A source that dies in its incoming predecessor takes the destination's slot, making its spill the edge transfer; every other edge becomes a COPY in the predecessor, where the allocator often coalesces it away. A PHI whose destination could be read on another path out of a predecessor is lowered through a virtual register, as PHIElimination does.
• A tied use that dies at the instruction takes over the tied def's register when its class contains it, and is otherwise copied into it, matching TwoAddressInstructionPass.
• REG_SEQUENCE and INSERT_SUBREG expand to subregister COPYs.

Targets opt in with TargetMachine::setEnableSSAFastRegAlloc(); X86 and AArch64 do. AMDGPU keeps the standard pipeline, anchoring SILowerControlFlow and SIWholeQuadMode on the skipped pass IDs. The SSA path requires the incoming MIR to carry IsSSA, so partial pipelines follow the MIR they are given; -regalloc-fast-ssa overrides the target default in either direction, and =0 restores byte-identical output.

clang -O0: codegen for lld/ELF/Driver.cpp takes 276.6ms -> 264.2ms (-4.5%). On -O2 bitcode through llc -O0, where PHIs are plentiful, .text -1.10% (Driver.cpp) and -1.89% (ScalarEvolution.cpp); AArch64 -0.16%. CTMark at -O0 builds, runs and verifies 10/10.

RFC: https://discourse.llvm.org/t/make-regallocfast-consume-machineir-in-ssa-form/91607