OpenRTL profile: MIT hardware accelerators, engineering evidence, and custom ASIC/FPGA development.
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Oct 18, 2026
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openrtl
Here are 17 public repositories matching this topic...
MIT-licensed Goldilocks coset low-degree extension (LDE) hardware accelerator. Chisel source and generated SystemVerilog. | MIT 开源 Goldilocks 陪集低度扩展硬件加速器，提供 Chisel 源码与生成的 SystemVerilog。
chisel rtl systemverilog stark hardware-acceleration zero-knowledge ntt goldilocks openrtl low-degree-extension
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Oct 17, 2026 - SystemVerilog
MIT-licensed Goldilocks Poseidon2 sponge hashing and digest compression hardware accelerator. Chisel source and generated SystemVerilog. | MIT 开源 Goldilocks Poseidon2 海绵哈希与摘要压缩硬件加速器，提供 Chisel 源码与生成的 SystemVerilog。
cryptography sponge chisel rtl systemverilog hardware-acceleration zero-knowledge goldilocks poseidon2 openrtl
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Oct 17, 2026 - SystemVerilog
MIT-licensed Goldilocks Poseidon2 Merkle tree and path verification hardware accelerator. Chisel source and generated SystemVerilog. | MIT 开源 Goldilocks Poseidon2 Merkle 建树与路径验证硬件加速器，提供 Chisel 源码与生成的 SystemVerilog。
cryptography chisel rtl systemverilog merkle-tree hardware-acceleration zero-knowledge goldilocks poseidon2 openrtl
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Oct 17, 2026 - SystemVerilog
MIT-licensed Goldilocks quadratic-extension vector arithmetic hardware accelerator. Chisel source and generated SystemVerilog. | MIT 开源 Goldilocks 二次扩域向量运算硬件加速器，提供 Chisel 源码与生成的 SystemVerilog。
chisel rtl systemverilog hardware-acceleration zero-knowledge goldilocks finite-field vector-processing openrtl extension-field
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Oct 17, 2026 - SystemVerilog
MIT-licensed Goldilocks finite-field vector arithmetic and dot-product hardware accelerator. Chisel source and generated SystemVerilog. | MIT 开源 Goldilocks 素域向量运算与点积硬件加速器，提供 Chisel 源码与生成的 SystemVerilog。
chisel rtl modular-arithmetic systemverilog hardware-acceleration zero-knowledge goldilocks finite-field vector-processing openrtl
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Oct 17, 2026 - SystemVerilog
JPEG XL lossless hardware encoder: Chisel/SystemVerilog, tests and reusable RISC-V adapters. MIT original code.
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Oct 23, 2026 - SystemVerilog
MIT-licensed PNG encoder/decoder in Chisel and SystemVerilog. | MIT许可PNG编解码硬件，含Chisel源码与SystemVerilog。
png chisel rtl image-compression systemverilog hardware-acceleration deflate lossless-compression openrtl
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Oct 17, 2026 - SystemVerilog
MIT-licensed Goldilocks binary FRI folding hardware accelerator. Chisel source and generated SystemVerilog. | MIT 开源 Goldilocks 二元 FRI 求值表折叠硬件加速器，提供 Chisel 源码与生成的 SystemVerilog。
chisel rtl systemverilog stark hardware-acceleration polynomial-arithmetic zero-knowledge fri goldilocks openrtl
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Oct 17, 2026 - SystemVerilog
MIT-licensed ZK hardware accelerator catalogue: 11 standalone Chisel/SystemVerilog operator families with inspectable engineering evidence. | MIT 开源 ZK 硬件加速器目录：汇集 11 类独立 Chisel/SystemVerilog 算子及可检查的工程证据。
cryptography chisel rtl systemverilog msm stark hardware-acceleration zero-knowledge ntt sumcheck poseidon2 openrtl
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Oct 17, 2026 - Python
MIT-licensed image-codec hardware catalogue: standalone Chisel/SystemVerilog designs for ASIC/FPGA integration. | MIT 开源图像编解码硬件目录，汇集可独立集成的 Chisel 源码与 SystemVerilog 项目。
png image-processing chisel rtl image-compression systemverilog hardware-acceleration lossless-compression openrtl
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Oct 23, 2026 - Python
MIT-licensed Goldilocks Sumcheck round and multilinear evaluation hardware accelerator. Chisel source and generated SystemVerilog. | MIT 开源 Goldilocks Sumcheck 轮计算与多线性求值硬件加速器，提供 Chisel 源码与生成的 SystemVerilog。
chisel rtl systemverilog hardware-acceleration polynomial-arithmetic zero-knowledge goldilocks sumcheck openrtl multilinear-extension
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Oct 17, 2026 - SystemVerilog
MIT-licensed Goldilocks batch inversion and division hardware accelerator. Chisel source and generated SystemVerilog. | MIT 开源 Goldilocks 批量求逆与除法硬件加速器，提供 Chisel 源码与生成的 SystemVerilog。
chisel rtl systemverilog hardware-acceleration zero-knowledge goldilocks modular-inverse finite-field batch-inversion openrtl
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Oct 17, 2026 - SystemVerilog
MIT-licensed 1G Ethernet RTL, Chisel/SystemVerilog and OpenNIC Linux driver. | MIT 原创千兆以太网RTL、Chisel/SystemVerilog及OpenNIC Linux驱动。
fpga chisel riscv rtl ethernet systemverilog linux-driver network-interface gigabit-ethernet openrtl
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Oct 22, 2026 - SystemVerilog
MIT-licensed Goldilocks NTT/INTT hardware accelerator. Chisel source and generated SystemVerilog. | MIT 开源 Goldilocks 数论变换与逆变换硬件加速器，提供 Chisel 源码与生成的 SystemVerilog。
chisel rtl systemverilog hardware-acceleration number-theoretic-transform polynomial-arithmetic zero-knowledge ntt goldilocks openrtl
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Oct 17, 2026 - SystemVerilog
MIT-licensed Goldilocks Poseidon2 12-element permutation hardware accelerator. Chisel source and generated SystemVerilog. | MIT 开源 Goldilocks Poseidon2 十二元素置换硬件加速器，提供 Chisel 源码与生成的 SystemVerilog。
cryptography hash chisel rtl systemverilog hardware-acceleration zero-knowledge goldilocks poseidon2 openrtl
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Oct 17, 2026 - SystemVerilog
MIT-licensed BN254-G1 multi-scalar multiplication (MSM) hardware accelerator. Chisel source and generated SystemVerilog. | MIT 开源 BN254-G1 椭圆曲线多标量乘法硬件加速器，提供 Chisel 源码与生成的 SystemVerilog。
cryptography chisel rtl systemverilog msm hardware-acceleration zero-knowledge elliptic-curve bn254 multi-scalar-multiplication openrtl
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Oct 17, 2026 - SystemVerilog
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