computer-arithmetic

Stochastic Computing for Deep Neural Networks

Design and implementation of RISC-V processor with a pipelined datapath, controller, and hazard unit.

Generating Posit-Based Accelerators With High-Level Synthesis

Open, bit-reproducible low-precision number format (b-posit / AI-Posit) for AI inference — 30–50% less memory, with results identical to the bit on any GPU, CPU, or RISC-V. Reference + conformance suite + CORE-ET RTL

Code for reproducing CoNGA 2022 results on posit arithmetic operators

Bit-exact NVIDIA MUFU/SFU model, exhaustively verified on A100, Ada and Blackwell GPUs.

POPiX: Floating to Fixed-Point Code Generator

Assignment codes for Introduction to Numerical Analysis (2020, FGV-EMAp).

A 32 bit Booth Encoded Wallace Tree Multiplier in Verilog HDL.

Computer Architecture: 01:198:211 This course covers the fundamental issues in the design of modern computer systems, including the design and implementation of key hardware components such as the processor, memory, and I/O devices, and the software/hardware interface.

Design and implementation of RISC-V processor with a multi-cycle datapath and controller.

Code for reproducing CoNGA 2023 results on approximate posit arithmetic

Design and implementation of RISC-V processor with a single-cycle datapath and controller.

Aritmética computacional: conversiones entre binario, decimal y hexadecimal; representación en signo-magnitud, complemento a 2 y estándar de punto flotante IEEE 754. Tecnología en Computadores, Ingeniería Informática.

Proyecto

IEEE 754 half-precision (16-bit) floating-point multiplier

Course Taken @ UCMerced [2021]

Bounded Posits at IEEE Tensor-Core Throughput on Commodity NVIDIA Blackwell, with Bit-Exact Reproducibility

Radix-4 Modified Booth multiplier with a hand-built Dadda tree and Bewick sign extension, in SystemVerilog. It is integrated as the mantissa multiplier of an IEEE 754 half-precision FPU, and five Synopsys DC strategies are compared (up to 473.9 MHz) on NanGate 45nm.

Bit-exact replicas of NVIDIA tensor-core arithmetic in RTL: one parametrised T-FDPA unit from Volta to RTX Blackwell (MXFP4/NVFP4 included) and GEMM arrays on an AMD Kria KV260, checked byte for byte against real GPUs.