Feature: Complete RISC-V baremetal support with automated qemu emulation by sshahi-mips · Pull Request #3254 · tensorflow/tflite-micro

sshahi-mips · 2025-11-17T05:15:49Z

Solves issue #3253

Adds full bare-metal RISC-V 32-bit support for TensorFlow Lite Micro, including a minimal bootloader, linker script, UART driver logging, stubs (all under tensorflow/lite/micro/riscv32_baremetal/), and a new target (riscv32_baremetal_makefile.inc) with QEMU full-system emulation. This enables running TFLM examples without any OS dependencies and improves embedded portability and testability.

…under qemu emulation. This update introduces a complete bare-metal support for TensorFlow Lite Micro on riscv32 baremetal toolchain using system mode qemu, including: - A minimal bootloader: start.s initializes stack and frame pointers for program entry. - Linker script: linker.ld defines memory layout and section mapping. - Stub handling: stubs.cc provides minimal syscall stubs for bare-metal builds. - UART driver: debug_log.cc implements UART-based logging for TFLM. - Lightweight printf: lightweight_snprintf supports %s, %d, and %p without libc. - Documentation: README.md describes build and run steps for the riscv32_baremetal target.

… to final baremetal executable.

…m emulation for any example.

veblush

Thank you for the PR!

veblush · 2025-11-19T22:02:24Z

tensorflow/lite/micro/riscv32_baremetal/README.md

@@ -0,0 +1,38 @@
+### **RISC-V 32-Bit Bare-Metal Support**


The current setup appears to be highly specific to QEMU. If this is the case, perhaps we should rename riscv32_baremetal to riscv32_qemu for better clarity.

veblush · 2025-11-19T22:02:36Z

tensorflow/lite/micro/riscv32_baremetal/debug_log.cc

@@ -0,0 +1,72 @@
+/* Copyright 2023 The TensorFlow Authors. All Rights Reserved.


veblush · 2025-11-19T22:07:16Z

tensorflow/lite/micro/riscv32_baremetal/debug_log.cc

+#include <stdio.h>  
+#include "tensorflow/lite/micro/riscv32_baremetal/lightweight_snprintf.cc"
+
+// UART definitions- Datasheet: https://pdos.csail.mit.edu/6.S081/2024/lec/16550.pdf


How about using Semihosting instead of having UART support here?

@veblush I dont think we should have any specific UART support here, since this PR is for generic riscv32. Any specific UART support should be part of the application, not TFLM. This file should look identical to tensorflow/lite/micro/riscv32_generic/debug_log.cc with the std::fputs replaced with an external uart_puts which is supplied by the application. Also there should be documentation explaining the application requirements for using riscv32-baremetal (stub methods, uart, etc.)

veblush · 2025-11-19T22:08:08Z

tensorflow/lite/micro/riscv32_baremetal/stubs.cc

@@ -0,0 +1,40 @@
+extern "C" {


This might not be necessary if Semihosting is used?

veblush · 2025-11-19T22:09:58Z

tensorflow/lite/micro/tools/make/Makefile

 	-o $@ $< \
 	$(MICROLITE_LIB_PATH) $(LDFLAGS) $(MICROLITE_LIBS)

+# Build rules and object setup for the RISC-V 32-bit bare-metal target,


The primary Makefile should only contain common definitions. All platform-specific configurations must be moved into their respective target makefiles.

veblush · 2025-11-19T22:13:06Z

tensorflow/lite/micro/tools/make/targets/riscv32_baremetal_makefile.inc

+# List of available examples
+EXAMPLES := person_detection hello_world micro_speech person_detection_test hello_world_test micro_speech_test dtln_test
+
+# Run a given example in QEMU using test_with_qemu.sh
+$(EXAMPLES):
+	@$(TEST_SCRIPT) system-riscv32 - gen/riscv32_baremetal_x86_64_default_gcc/bin/$@ non_test_binary riscv32_baremetal


This doesn't seem like the best place for the examples instructions. Why do we need this?

veblush · 2025-11-19T22:13:22Z

tensorflow/lite/micro/tools/make/targets/riscv32_baremetal_makefile.inc

+TARGET_TOOLCHAIN_PREFIX := riscv32-unknown-elf-
+
+# Toolchain Path 
+TARGET_TOOLCHAIN_ROOT := /home/mips/riscv32/bin/


I think this is the test code?

@veblush The toolchain download should occur here as per tensorflow/lite/micro/tools/make/targets/riscv32_generic_makefile.inc

ddavis-2015 · 2025-11-20T18:36:07Z

tensorflow/lite/micro/riscv32_baremetal/debug_log.cc

+  char buffer[256];  // Temporary buffer for formatted string
+  int len = mini_vsnprintf(buffer, sizeof(buffer), format, args);
+  if (len > 0) {
+    UART0_FCR = UARTFCR_FFENA;


Should be part of uart_puts method.

ddavis-2015 · 2025-11-20T18:41:45Z

tensorflow/lite/micro/riscv32_baremetal/debug_log.cc

+#include <stdio.h>  
+#include "tensorflow/lite/micro/riscv32_baremetal/lightweight_snprintf.cc"
+
+// UART definitions- Datasheet: https://pdos.csail.mit.edu/6.S081/2024/lec/16550.pdf


@veblush I dont think we should have any specific UART support here, since this PR is for generic riscv32. Any specific UART support should be part of the application, not TFLM. This file should look identical to tensorflow/lite/micro/riscv32_generic/debug_log.cc with the std::fputs replaced with an external uart_puts which is supplied by the application. Also there should be documentation explaining the application requirements for using riscv32-baremetal (stub methods, uart, etc.)

ddavis-2015 · 2025-11-20T18:45:59Z

tensorflow/lite/micro/riscv32_baremetal/debug_log.cc

+extern "C" void DebugLog(const char* format, va_list args) {
+#ifndef TF_LITE_STRIP_ERROR_STRINGS
+  char buffer[256];  // Temporary buffer for formatted string
+  int len = mini_vsnprintf(buffer, sizeof(buffer), format, args);


Why are we using this mini_vsnprintf? The eyalroz_printf code should be used here (as per tensorflow/lite/micro/riscv32_generic/debug_log.cc). If the application developer wants a different printf library, they can define their own DebugLog and DebugVsnprintf. Slapping a weak attribute on these two methods in debug_log.cc for bare-metal should be sufficient for that to happen.

ddavis-2015 · 2025-11-20T18:47:02Z

tensorflow/lite/micro/riscv32_baremetal/lightweight_snprintf.cc

@veblush I'm not seeing why this should be part of TFLM.

ddavis-2015 · 2025-11-20T18:52:04Z

tensorflow/lite/micro/riscv32_baremetal/stubs.cc

@veblush Don't see how any of the stubs should be part of TFLM (except _exit). No example application or unit test should require any of these stubs, nor should they currently be calling any C or C++ standard library code that would use these stubs. The exception I think would be _exit as a return from main may trigger _exit as part of the C/C++ runtime.

ddavis-2015 · 2025-11-20T19:01:48Z

tensorflow/lite/micro/testing/test_with_qemu.sh

-qemu-${1} -cpu ${2} ${3} 2>&1 | tee ${MICRO_LOG_FILENAME}
+if [[ "${5}" == "riscv32_baremetal" ]]; then
+    # unified call
+    qemu-${1} -nographic -M virt -bios none -kernel ${3} 2>&1 | tee ${MICRO_LOG_FILENAME}


@veblush If something beyond apt install qemu-system is involved in running this command or some other Linux OS configuration is required, this should be documented.

ddavis-2015 · 2025-11-20T19:13:13Z

tensorflow/lite/micro/tools/make/targets/riscv32_baremetal_makefile.inc

+TARGET_TOOLCHAIN_PREFIX := riscv32-unknown-elf-
+
+# Toolchain Path 
+TARGET_TOOLCHAIN_ROOT := /home/mips/riscv32/bin/


@veblush The toolchain download should occur here as per tensorflow/lite/micro/tools/make/targets/riscv32_generic_makefile.inc

github-actions · 2026-02-10T10:25:46Z

This PR is being marked as stale due to inactivity. Remove the stale label or comment to prevent closure in 5 days.

github-actions · 2026-02-16T10:25:25Z

This PR is being closed because it has been marked as stale for 5 days with no further activity.

sshahi-mips added 4 commits November 16, 2025 19:22

Add target-specific Makefile for RISC-V 32-bit bare-metal toolchain.

3fd7a8d

Integrate start.s and stubs.cc into Makefile to compile and link them…

81f2327

… to final baremetal executable.

Automate the qemu-system-riscv32 call from here to support full syste…

816dbd6

…m emulation for any example.

sshahi-mips requested a review from a team as a code owner November 17, 2025 05:15

veblush self-requested a review November 19, 2025 22:00

veblush reviewed Nov 19, 2025

View reviewed changes

ddavis-2015 reviewed Dec 11, 2025

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github-actions bot added the Stale label Feb 10, 2026

github-actions bot closed this Feb 16, 2026

		@@ -0,0 +1,72 @@
		/* Copyright 2023 The TensorFlow Authors. All Rights Reserved.

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sshahi-mips commented Nov 17, 2025

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