docs: fix memory-map table to show infra reserve at top of IPA#79
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The Memory Layout table in internals.md showed the page-table pool, shim code, and shim data at low addresses (0x10000-0x3FFFFF), a legacy layout. The code (compute_infra_layout in src/core/guest.c) anchors the infra reserve at [interp_base - INFRA_RESERVE, interp_base), in the dead zone above mmap_limit, so EL0 binaries are free to load at low addresses without colliding with the runtime. Rewrite the table to split low fixed addresses from the interp_base-anchored high reserve, and describe the reserve's internal layout (null guard, page table pool, shim code sharing the pool's tail 2 MiB block, shim data) to match src/core/guest.h. Numbers reflect the grown 16 MiB reserve / ~13.9 MiB pool from sysprog21#75; this doc PR should land together with or after that change.
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Summary
The Memory Layout table in
docs/internals.mdshowed the page-table pool, shim code, and shim data at low addresses (0x10000–0x3FFFFF) — a legacy layout. The code (compute_infra_layoutinsrc/core/guest.c) anchors the infrastructure reserve at[interp_base - INFRA_RESERVE, interp_base), in the dead zone abovemmap_limit, so EL0 binaries are free to load at low addresses without colliding with the runtime.This is the doc-cleanup follow-up @jserv flagged on #75 ("carries a pre-existing memory-map table showing a legacy layout with the infra reserve at LOW addresses; the actual code places it at the top of IPA. Worth a separate doc-cleanup PR"), kept out of #75 as requested.
Changes
interp_base-anchored high reserve.src/core/guest.h.MAP_ANON) so the reservation costs no host RAM.Ordering
Numbers reflect the grown 16 MiB reserve / ~13.9 MiB pool from #75, not current
main(4 MiB / 960 KiB). This PR should land together with or after #75; the two touch different files (#75→guest.h/main.c, this →internals.md), so no merge conflict.Docs-only; no code change.