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ArmPattern: bitfield, shift and extend aliases #9
Description
All aliases of UBFM/SBFM/BFM (or EXTR) with computed immr/imms; wildcards today.
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LSL/LSR/ASR Rd, Rn, #imm(LSL #n=UBFMimmr = -n mod size, imms = size-1-n) andROR #imm(EXTR) - Register shifts
LSL/LSR/ASR/ROR Rd, Rn, Rm(LSLVetc.) -
UBFX/SBFX/UBFIZ/SBFIZ/BFI/BFXIL -
SXTB/SXTH/SXTW/UXTB/UXTH
#? should leave immr/imms open (LSL Rd, Rn, #? can't pin either field). Like MOV, encode them the way assemblers do and check against clang in tests/test_arm.cpp.
🤖 Generated with Claude Code
Activity
scizzydo commentedon Oct 12, 2026
Addressed in #12 (
parse_bitfield<kind>,parse_shift):LSL/LSR/ASR #imm(UBFM/SBFM) andROR #imm(EXTR Rd, Rn, Rn); the register formsLSL/LSR/ASR/ROR Rd, Rn, RmandLSLVetc.UBFX/SBFX/BFXIL/UBFIZ/SBFIZ/BFI, rawUBFM/SBFM/BFM/EXTR, andSXTB/SXTH/SXTW/UXTB/UXTH.LSR/ASR #?keep imms pinned (exact);LSL #?has to open immr and imms, so it also matches other UBFM forms (documented). A field computed from a?is left open (UBFX #?, #8leaves imms open). With a bare?register, the 32- and 64-bit encodings are both computed and only the bits they share stay pinned; if only one size fits (LSL ?, ?, #40), that one is used.SXTW W0, W1andUXTB X0, W1give mask 0. All encodings were checked against clang.🤖 Generated with Claude Code