ArmPattern: remaining load/store forms (signed byte/halfword, exclusive, acquire/release)

The new parse_load_store<op, scale, unscaled> in ArmPattern.hpp makes most of these one table row each.

LDRSB/LDRSH and LDURSB/LDURSH: opc is 10 for an X destination and 11 for W, so bit 22 comes from Rt (like bit 30 does for LDR). Needs a small tweak to parse_load_store.
LDPSW, LDNP/STNP.
Exclusive and acquire/release: LDXR/STXR/LDAXR/STLXR (+ B/H forms), LDAR/STLR, LDAPR.
LSE atomics: CAS/CASA/CASAL, LDADD/LDADDAL, SWP, STADD (alias).

🤖 Generated with Claude Code

Addressed in #12:

LDRSB/LDRSH and LDURSB/LDURSH: parse_load_store gained a sign_extend flag; bit 22 comes from Rt (W 1, X 0) and ? leaves it open.
LDPSW (X only), LDNP/STNP (signed offset only; pre/post-index gives mask 0), via parse_ldp<opc, no_allocate>.
LDXR/STXR/LDAXR/STLXR/LDAR/STLR/LDAPR with their B/H forms, and LDXP/STXP/LDAXP/STLXP: size comes from Rt (not from Ws or Xn).
LSE: CAS, SWP, LD<op>, ST<op> for ADD/CLR/EOR/SET/SMAX/SMIN/UMAX/UMIN with every A/L/AL and B/H suffix, read from the mnemonic (parse_atomic) rather than ~130 table rows. The mnemonic buffer grew to 15 characters for LDSMAXALB.

🤖 Generated with Claude Code

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