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ArmPattern: floating-point/SIMD loads, stores and FMOV #7
Description
LDR/STR/LDUR/STUR/LDP/STP only take W/X registers. With B/H/S/D/Q registers the line is a wildcard (mask 0, so the IDA plugin warns); before the scanner-overhaul branch they were silently encoded as integer loads and never matched.
Common in practice: STP D9, D8, [SP,#-0x20]! / LDP D9, D8, ... in prologues and epilogues, LDP Q0, Q1, [X1] / STP Q0, Q1, ... struct copies, LDR S0, [X0,#8] float members.
- Single-register forms: V bit 26 set; size + opc bit 23 select B/H/S/D/Q (Q: size 00, opc 1x); the unsigned offset is scaled by the access size. Extend
parse_load_storeinArmPattern.hpp. - Pairs: opc 00 S / 01 D / 10 Q with V = 1; imm7 scaled by 4/8/16. Extend
parse_ldp. -
FMOV(register, general-purpose to/from FP, and the 8-bit immediate form). - Literal
LDR S0/D0/Q0, #offset.
🤖 Generated with Claude Code
Activity
scizzydo commentedon Oct 12, 2026
Addressed in #12:
LDR/STR/LDUR/STURwith B/H/S/D/Q registers: V (bit 26), size and opc bit 23 (Q) come from Rt, and the offset is scaled by the access size (pre/post-index and register-offset forms included).LDP/STP(andLDNP/STNP) with S/D/Q, imm7 scaled by 4/8/16.LDR S/D/Q, #offset.FMOV: register, general-purpose to/from FP (S/W, D/X, H/W/X), and immediates such as#1.0,#-2.5,#0.125(all 256 imm8 values compared exactly).#0.0encodes as FMOV from the zero register; a value that isn't representable gives mask 0.?load/store register still means W or X (it would otherwise also match LDRB/LDRSB); useD?,Q?, etc. for FP registers./d: FP loads after ADRP (ADRP X8+LDR D0, [X8,#lo]) and FP literal loads resolve.🤖 Generated with Claude Code