ArmPattern: TBZ/TBNZ and exception instructions (SVC, BRK, UDF, HLT)

These are wildcards today (a64_encode_instruction returns mask 0).

TBZ / TBNZ Rt, #bit, #offset: b5 is bit 31, b40 is bits 19-23, imm14 is bits 5-18. Base 0x36000000 / 0x37000000. Wildcards: Rt, #? bit, #? offset. A W register implies bit < 32 (b5 = 0); ? leaves b5 open.
SVC / BRK / HLT / UDF #imm16: imm16 at bit 5 (UDF: bits 0-15). Bases 0xD4000001, 0xD4200000, 0xD4400000, 0x00000000. #? leaves the immediate open. SVC #0x80 is the Apple syscall, useful for anti-debug patterns.

Add CONCRETE/WILDCARD rows in tests/test_arm.cpp and the README's supported list.

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Addressed in #12:

TBZ/TBNZ Rt, #bit, #offset (parse_tbz): a W register (or a bit below 32) sets b5 to 0, #? leaves the bit open (b5 stays 0 for W), and X?/? with #? leaves b5 open. A bit out of range for the register gives mask 0.
SVC/HVC/SMC/BRK/HLT #imm16 (bit 5) and UDF #imm16 (bit 0) via parse_imm16<shift>; #? leaves the immediate open.
/d resolves TBZ/TBNZ targets (imm14).
Tests: CONCRETE/WILDCARD rows checked against llvm-mc and Apple's assembler; docs/arm64.md updated.

🤖 Generated with Claude Code

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