ArmPattern: conditional select/compare, multiply/divide and remaining ALU aliases

Wildcards today:

CSEL/CSINC/CSINV/CSNEG Rd, Rn, Rm, cond (cond at bits 12-15; ? leaves it open). Reuse the conditions table from B.cond.
Aliases CSET/CSETM/CINC/CINV/CNEG: these store the inverted condition (cond ^ 1).
CCMP/CCMN (register and 5-bit immediate forms, #nzcv).
MADD/MSUB/MUL/MNEG, SMULL/UMULL/SMADDL/UMADDL, SMULH/UMULH, UDIV/SDIV.
Logical with inverted operand: BIC/BICS/ORN/EON (N bit 21 = 1; parse_orr forces 0), and MVN (ORN Rd, ZR, Rm).
NEG/NEGS (SUB(S) Rd, ZR, Rm), ADC/ADCS/SBC/SBCS.

🤖 Generated with Claude Code

Addressed in #12:

CSEL/CSINC/CSINV/CSNEG, condition at bits 12-15 via the new shared parse_cond (also used by B.cond); ? leaves it open.
CSET/CSETM/CINC/CINV/CNEG store the inverted condition; AL/NV give mask 0. With X?, Rm can't be tied to Rn (documented).
CCMP/CCMN, register and imm5 forms, #nzcv.
MADD/MSUB/MUL/MNEG, SMADDL/UMADDL/SMSUBL/UMSUBL, SMULL/UMULL/SMNEGL/UMNEGL, SMULH/UMULH, UDIV/SDIV.
BIC/BICS/ORN/EON (parse_orr takes N from the table; the immediate form gives mask 0), MVN, NEG/NEGS, ADC/ADCS/SBC/SBCS, NGC/NGCS (parse_zr now inserts the zero register at the destination or first source).
Also fixed: a ? shift type (ORR X0, X1, X2, ?, ADD ..., ?) used to pin LSL; it now leaves the shift type open.

🤖 Generated with Claude Code

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