Skip to content

Add f16 inline ASM support for RISC-V#126530

Merged
bors merged 1 commit intorust-lang:masterfrom
beetrees:f16-inline-asm-riscv
Jun 22, 2024
Merged

Add f16 inline ASM support for RISC-V#126530
bors merged 1 commit intorust-lang:masterfrom
beetrees:f16-inline-asm-riscv

Conversation

@beetrees
Copy link
Copy Markdown
Contributor

This PR adds f16 inline ASM support for RISC-V. A FIXME is left for f128 support as LLVM does not support the required Q (Quad-Precision Floating-Point) extension yet.

Relevant issue: #125398
Tracking issue: #116909

@rustbot label +F-f16_and_f128

Loading
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

F-f16_and_f128 `#![feature(f16)]`, `#![feature(f128)]` S-waiting-on-bors Status: Waiting on bors to run and complete tests. Bors will change the label on completion. T-compiler Relevant to the compiler team, which will review and decide on the PR/issue.

Projects

None yet

Development

Successfully merging this pull request may close these issues.

9 participants