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Add the "qcom,qcs615-qspi" compatible string to the Qualcomm QSPI device- tree binding to enable QCS615-based platforms to use the existing QSPI controller binding. Signed-off-by: Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260324-spi-nor-v1-1-3efe59c1c119@oss.qualcomm.com/
The QSPI controller has two interconnect paths: 1. qspi-config: CPU to QSPI controller for register access 2. qspi-memory: QSPI controller to memory for DMA operations Currently, the driver only manages the qspi-config path. Add support for the qspi-memory path to ensure proper bandwidth allocation for QSPI data transfers to/from memory. Enable and disable both paths during runtime PM transitions. Signed-off-by: Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260324-spi-nor-v1-2-3efe59c1c119@oss.qualcomm.com/
The Talos (QCS615) platform includes a QSPI controller used for accessing external flash storage. Add the QSPI OPP table, TLMM pinmux entries, and the QSPI controller node to enable support for this hardware. Signed-off-by: Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260324-spi-nor-v1-3-3efe59c1c119@oss.qualcomm.com/
The QCS615 Ride board has a SPI-NOR flash connected to the QSPI controller on CS0. Enable the QSPI controller and add the corresponding SPI-NOR flash node to allow the system to access it. Signed-off-by: Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260324-spi-nor-v1-4-3efe59c1c119@oss.qualcomm.com/
Check why is below check failing ? Make sure mainline SI in CR has an associated github PR. qcom-6.18.y-checkFailing after 2s — Change Requests Validation Check |
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This Feature Request proposes enabling QSPI NOR flash support in the High-Level Operating System (HLOS) to allow direct access and management of QSPI NOR devices from the OS layer.
CRs-Fixed: 4476282