FROMLIST: v4: Add explicit clock vote and enable power-domain for QCOM-ICE#829
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arakshit011 wants to merge 21 commits intoqualcomm-linux:tech/security/icefrom
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FROMLIST: v4: Add explicit clock vote and enable power-domain for QCOM-ICE#829arakshit011 wants to merge 21 commits intoqualcomm-linux:tech/security/icefrom
arakshit011 wants to merge 21 commits intoqualcomm-linux:tech/security/icefrom
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…and iface clk This reverts commit ee496ca. Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
… clk for ice node This reverts commit 6675f55. Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
… clk for ice node This reverts commit 4622e9a. Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
… clk for ice node This reverts commit 1434fd8. Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
… clk for ice node This reverts commit a1310e6. Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
… clk for ice node This reverts commit e86738a. Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
… clk for ice node This reverts commit e670e83. Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
… clk for ice node This reverts commit 4e48c91. Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
… clk for ice node This reverts commit a207c39. Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
…voting calls for ICE This reverts commit 725a9c8. Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
… iface clk The DT bindings for inline-crypto engine do not specify the UFS_PHY_GDSC power-domain and iface clock. Without enabling the iface clock and the associated power-domain the ICE hardware cannot function correctly and leads to unclocked hardware accesses being observed during probe. Fix the DT bindings for inline-crypto engine to require the UFS_PHY_GDSC power-domain and iface clock for new devices (Eliza and Milos) introduced in the current release (7.0) with yet-to-stabilize ABI, while preserving backward compatibility for older devices. Link: https://lore.kernel.org/all/20260323-qcom_ice_power_and_clk_vote-v4-1-e36044bbdfe9@oss.qualcomm.com/ Fixes: 618195a7ac3df ("dt-bindings: crypto: qcom,inline-crypto-engine: Document the Eliza ICE") Fixes: 85faec1 ("dt-bindings: crypto: qcom,inline-crypto-engine: document the Milos ICE") Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com> Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
Since Qualcomm inline-crypto engine (ICE) is now a dedicated driver de-coupled from the QCOM UFS driver, it explicitly votes for its required clocks during probe. For scenarios where the 'clk_ignore_unused' flag is not passed on the kernel command line, to avoid potential unclocked ICE hardware register access during probe the ICE driver should additionally vote on the 'iface' clock. Also update the suspend and resume callbacks to handle un-voting and voting on the 'iface' clock. Link: https://lore.kernel.org/all/20260323-qcom_ice_power_and_clk_vote-v4-2-e36044bbdfe9@oss.qualcomm.com/ Fixes: 2afbf43 ("soc: qcom: Make the Qualcomm UFS/SDCC ICE a dedicated driver") Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com> Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
… for ice node Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for its own resources. Before accessing ICE hardware during probe, to avoid potential unclocked register access issues (when clk_ignore_unused is not passed on the kernel command line), in addition to the 'core' clock the 'iface' clock should also be turned on by the driver. This can only be done if the GCC_UFS_PHY_GDSC power domain is enabled. Specify both the GCC_UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for kaanapali. Link: https://lore.kernel.org/all/20260323-qcom_ice_power_and_clk_vote-v4-3-e36044bbdfe9@oss.qualcomm.com/ Fixes: 2eeb576 ("arm64: dts: qcom: Introduce Kaanapali SoC") Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com> Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
…r ice node Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for its own resources. Before accessing ICE hardware during probe, to avoid potential unclocked register access issues (when clk_ignore_unused is not passed on the kernel command line), in addition to the 'core' clock the 'iface' clock should also be turned on by the driver. This can only be done if the UFS_PHY_GDSC power domain is enabled. Specify both the UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for lemans. Link: https://lore.kernel.org/all/20260323-qcom_ice_power_and_clk_vote-v4-4-e36044bbdfe9@oss.qualcomm.com/ Fixes: 96272ba ("arm64: dts: qcom: sa8775p: enable the inline crypto engine") Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com> Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
…r ice node Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for its own resources. Before accessing ICE hardware during probe, to avoid potential unclocked register access issues (when clk_ignore_unused is not passed on the kernel command line), in addition to the 'core' clock the 'iface' clock should also be turned on by the driver. This can only be done if the GCC_UFS_PHY_GDSC power domain is enabled. Specify both the GCC_UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for monaco. Link: https://lore.kernel.org/all/20260323-qcom_ice_power_and_clk_vote-v4-5-e36044bbdfe9@oss.qualcomm.com/ Fixes: cc9d29a ("arm64: dts: qcom: qcs8300: enable the inline crypto engine") Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com> Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
…r ice node Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for its own resources. Before accessing ICE hardware during probe, to avoid potential unclocked register access issues (when clk_ignore_unused is not passed on the kernel command line), in addition to the 'core' clock the 'iface' clock should also be turned on by the driver. This can only be done if the UFS_PHY_GDSC power domain is enabled. Specify both the UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for sc7180. Link: https://lore.kernel.org/all/20260323-qcom_ice_power_and_clk_vote-v4-6-e36044bbdfe9@oss.qualcomm.com/ Fixes: 858536d ("arm64: dts: qcom: sc7180: Add UFS nodes") Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com> Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
…r ice node Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for its own resources. Before accessing ICE hardware during probe, to avoid potential unclocked register access issues (when clk_ignore_unused is not passed on the kernel command line), in addition to the 'core' clock the 'iface' clock should also be turned on by the driver. This can only be done if the GCC_UFS_PHY_GDSC power domain is enabled. Specify both the GCC_UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for kodiak. Link: https://lore.kernel.org/all/20260323-qcom_ice_power_and_clk_vote-v4-7-e36044bbdfe9@oss.qualcomm.com/ Fixes: dfd5ee7 ("arm64: dts: qcom: sc7280: Add inline crypto engine") Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com> Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
…r ice node Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for its own resources. Before accessing ICE hardware during probe, to avoid potential unclocked register access issues (when clk_ignore_unused is not passed on the kernel command line), in addition to the 'core' clock the 'iface' clock should also be turned on by the driver. This can only be done if the UFS_PHY_GDSC power domain is enabled. Specify both the UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for sm8450. Link: https://lore.kernel.org/all/20260323-qcom_ice_power_and_clk_vote-v4-8-e36044bbdfe9@oss.qualcomm.com/ Fixes: 86b0aef ("arm64: dts: qcom: sm8450: Use standalone ICE node for UFS") Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com>Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
…r ice node Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for its own resources. Before accessing ICE hardware during probe, to avoid potential unclocked register access issues (when clk_ignore_unused is not passed on the kernel command line), in addition to the 'core' clock the 'iface' clock should also be turned on by the driver. This can only be done if the UFS_PHY_GDSC power domain is enabled. Specify both the UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for sm8550. Link: https://lore.kernel.org/all/20260323-qcom_ice_power_and_clk_vote-v4-9-e36044bbdfe9@oss.qualcomm.com/ Fixes: b8630c4 ("arm64: dts: qcom: sm8550: Add the Inline Crypto Engine node") Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com> Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
…r ice node Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for its own resources. Before accessing ICE hardware during probe, to avoid potential unclocked register access issues (when clk_ignore_unused is not passed on the kernel command line), in addition to the 'core' clock the 'iface' clock should also be turned on by the driver. This can only be done if the UFS_PHY_GDSC power domain is enabled. Specify both the UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for sm8650. Link: https://lore.kernel.org/all/20260323-qcom_ice_power_and_clk_vote-v4-10-e36044bbdfe9@oss.qualcomm.com/ Fixes: 10e0246 ("arm64: dts: qcom: sm8650: add interconnect dependent device nodes") Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com> Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
…r ice node Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for its own resources. Before accessing ICE hardware during probe, to avoid potential unclocked register access issues (when clk_ignore_unused is not passed on the kernel command line), in addition to the 'core' clock the 'iface' clock should also be turned on by the driver. This can only be done if the GCC_UFS_PHY_GDSC power domain is enabled. Specify both the GCC_UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for sm8750. Link: https://lore.kernel.org/all/20260323-qcom_ice_power_and_clk_vote-v4-11-e36044bbdfe9@oss.qualcomm.com/ Fixes: b1dac78 ("arm64: dts: qcom: sm8750: Add ICE nodes") Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com> Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
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When the kernel is booted without the 'clk_ignore_unused' and
'pd_ignore_unused' command‑line flags, votes for unused clocks and power
domains are dropped by the kernel post late_init and deferred probe
timeout. Depending on the relative timing between the ICE probe and the
kernel disabling the unused clocks and power domains occasional unclocked
register accesses or 'stuck' clocks are observed during QCOM‑ICE probe.
When the 'iface' clock is not voted on, unclocked register access would
be observed. On the other hand, if the associated power-domain for ICE
is not enabled, a 'stuck' clock is observed.
This patch series resolves both of these problems by adding explicit
power‑domain enablement and 'iface' clock‑vote handling to the QCOM‑ICE
driver.
The clock 'stuck' issue was first reported on Qualcomm RideSX4 (sa8775p)
platform: https://lore.kernel.org/all/ZZYTYsaNUuWQg3tR@x1/
Issue with unclocked ICE register access is easily reproducible on
on Qualcomm RB3Gen2 (kodiak) platform when 'clk_ignore_unused' is
not passed on the kernel command-line.
This patch series has been validated on: SM8650-MTP, RB3Gen2 and
Lemans-EVK.
This change reverts patch v1 and updates with the latest patchset v4 FROMLIST.
Link: https://lore.kernel.org/all/20260323-qcom_ice_power_and_clk_vote-v4-0-e36044bbdfe9@oss.qualcomm.com/
Signed-off-by: Harshal Dev harshal.dev@oss.qualcomm.com
Signed-off-by: Abhinaba Rakshit abhinaba.rakshit@oss.qualcomm.com