Tech/mm/gpu : Enable CLX support by shivrawa · Pull Request #1434 · qualcomm-linux/kernel-topics

Shivam Rawat (shivrawa) · 2026-06-29T18:00:14Z

It enables CLX support

In A8xx, the RSCC block is part of GPU's register space. Update the virtual base address of rscc to point to the correct address. Link: https://lore.kernel.org/all/20260512-glymur-gpu-dt-v3-1-84232dc21c03@oss.qualcomm.com/ Fixes: 50e8a55 ("drm/msm/a8xx: Add support for A8x GMU") Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>

Adreno X2-185 GPU found in Glymur chipsets belongs to the A8x family. It features a new slice architecture with 4 slices, significantly higher bandwidth throughput compared to mobile counterparts, raytracing support, and the highest GPU Fmax seen so far on an Adreno GPU (1850 Mhz), among other improvements. Update the dt bindings documentation to describe this GPU. Link: https://lore.kernel.org/all/20260513-glymur-gpu-dt-v4-2-f83832c3bc9a@oss.qualcomm.com/ Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>

…U SMMU Add interconnects property to the common SMMU properties and extend the sm8750 clock description section to also cover Glymur since it uses the same single "hlos" vote clock. Link: https://lore.kernel.org/all/20260513-glymur-gpu-dt-v4-3-f83832c3bc9a@oss.qualcomm.com/ Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>

Similar to a6xx_recover(), check the GX power domain status before accessing mmio in GX domain a8xx_recover(). Fixes: 288a932 ("drm/msm/adreno: Introduce A8x GPU Support") Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260427-gfx-clk-fixes-v2-5-797e54b3d464@oss.qualcomm.com

In A8x GPUs, the GX GDSC is moved to a separate block called GXCLKCTL which is under the GX power domain. Due to the way the support for this block is implemented in its driver, pm_runtime votes result in a vote on GX/GMxC/MxC rails from the APPS RSC. This is against the Adreno architecture which require GMU to be the sole voter of these collapsible rails on behalf of GPU, except during the GPU/GMU recovery. To align with this architectural requirement and to realize the power benefits of the IFPC feature, remove the GXPD votes during gmu resume and suspend. And during the recovery sequence, enable/disable the GXPD along with the 'synced_poweroff' genpd hint to force collapse this GDSC. Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260427-gfx-clk-fixes-v2-6-797e54b3d464@oss.qualcomm.com

There are stale RPMH votes (BCM votes) observed after GMU suspend. This is because the rpmh stop sequences are skipped during gmu suspend. Fix this and also move GMU to reset state to avoid any further activity. Link: https://lore.kernel.org/all/20260605-assorted-fixes-june-v1-1-2caa04f7287c@oss.qualcomm.com/ Fixes: f248d5d ("drm/msm/a6xx: Fix PDC sleep sequence") Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Signed-off-by: Shivam Rawat <shivrawa@qti.qualcomm.com>

During recovery, it is not safe to retire the hung submit before we recover the GPU. Retiring the submit triggers BO free and that can result in GPU pagefaults since the GPU may be actively accessing those BOs. To fix this, retire the submits after gpu recovery is complete in recover_worker(). Fixes: 1a370be ("drm/msm: restart queued submits after hang") Signed-off-by: Veeresh Bagale <vbagale@qti.qualcomm.com> Signed-off-by: Jie Zhang <jie.zhang@oss.qualcomm.com> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Link: https://lore.kernel.org/linux-arm-msm/20260605-assorted-fixes-june-v1-2-2caa04f7287c@oss.qualcomm.com

The GPUCC register list for A663 is incorrect, which can cause out-of-bounds register access during GPU state capture. Update it to use the correct register ranges. Fixes: 5773cce ("drm/msm/a6xx: Add support for A663") Signed-off-by: Veeresh Bagale <vbagale@qti.qualcomm.com> Signed-off-by: Jie Zhang <jie.zhang@oss.qualcomm.com> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Link: https://lore.kernel.org/linux-arm-msm/20260605-assorted-fixes-june-v1-3-2caa04f7287c@oss.qualcomm.com

A621 uses an incorrect GPUCC register list during state capture. The existing list matches A623/A663. Rename it accordingly and add a dedicated A621 GPUCC register list. Fixes: 11cdb81 ("drm/msm/a6xx: Fix gpucc register block for A621") Signed-off-by: Veeresh Bagale <vbagale@qti.qualcomm.com> Signed-off-by: Jie Zhang <jie.zhang@oss.qualcomm.com> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Link: https://lore.kernel.org/linux-arm-msm/20260605-assorted-fixes-june-v1-4-2caa04f7287c@oss.qualcomm.com

Once a hang is triggered by the msm_recovery test, the gpu error irq remains asserted and triggers an interrupt storm. In the worst case, this IRQ storm lands on the CPU core where the hangcheck timer is scheduled, blocking it from running. This eventually leads to CPU watchdog timeouts. To fix this, mask the gpu error irqs during msm_recovery test and enable them back during the recovery. Fixes: 5edf275 ("drm/msm: Add debugfs to disable hw err handling") Signed-off-by: Veeresh Bagale <vbagale@qti.qualcomm.com> Signed-off-by: Jie Zhang <jie.zhang@oss.qualcomm.com> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Link: https://lore.kernel.org/linux-arm-msm/20260605-assorted-fixes-june-v1-5-2caa04f7287c@oss.qualcomm.com

get_pid_task() increments the task reference count, but the corresponding put_task_struct() was missing in the else branch, leaking a reference on every GPU hang recovery. Fixes: 25654a1 ("drm/msm: Update global fault counter when faulty process has already ended") Signed-off-by: Veeresh Bagale <vbagale@qti.qualcomm.com> Signed-off-by: Jie Zhang <jie.zhang@oss.qualcomm.com> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Link: https://lore.kernel.org/linux-arm-msm/20260605-assorted-fixes-june-v1-6-2caa04f7287c@oss.qualcomm.com

Add support for Current Limit Extension (CLX) feature found on a few A8x GPUs. This feature is required to limit the peak current consumption to avoid HW spec violation on GX/MX rails. Add the necessary HFI interface support to pass the recommended CLX and IFF/PCLX limits tables to the GMU. Per-GPU configuration is consumed from the catalog entries. Link: https://lore.kernel.org/all/20260516-a8xx-clx-support-v1-0-62508bf651ac@oss.qualcomm.com/ Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Signed-off-by: Shivam Rawat <shivrawa@qti.qualcomm.com>

Add the A840 CLX domain table and the IFF/PCLX limits table to the catalog. With the HFI plumbing in place, this enables the Current Limit Extension (CLX) feature on Adreno 840. Limit : https://lore.kernel.org/all/20260516-a8xx-clx-support-v1-0-62508bf651ac@oss.qualcomm.com/ Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Shivam Rawat <shivrawa@qti.qualcomm.com>

Add the CLX domain table and the IFF/PCLX limits tables to the catalog to enable CLX feature support on Adreno X2-85 GPU present in the Glymur chipset. Link: https://lore.kernel.org/all/20260516-a8xx-clx-support-v1-0-62508bf651ac@oss.qualcomm.com/ Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Shivam Rawat <shivrawa@qti.qualcomm.com>

qlijarvis · 2026-06-29T18:53:29Z

PR #1434 — validate-patch

PR: #1434

Verdict	Issues	Detailed Report
⚠️	8	Full report

Final Summary

Lore link present: Partial — commits 1/3 and 3/3 have proper Link: tags; commit 2/3 has typo Limit : instead of Link:
Lore link matches PR commits: Cannot verify — the lore series (dated 2026-05-16) is not accessible via curl/b4; either the archive hasn't propagated yet or the date is incorrect. All three commits reference the same series cover letter URL.
Upstream patch status: In review — FROMLIST prefix indicates patches posted to mailing list but not yet merged into mainline. Commits 2/3 and 3/3 have Reviewed-by tags from Konrad Dybcio, suggesting active review.
PR present in qcom-next: Not checked — per constraints, no kernel tree access to verify integration status.

Verdict: ⚠️ — click to expand

🔍 Patch Validation

PR: #1434 - Add CLX (Current Limit Extension) support for A8x GPUs
Upstream commit: https://lore.kernel.org/all/20260516-a8xx-clx-support-v1-0-62508bf651ac@oss.qualcomm.com/ (series cover)
Verdict: ⚠️ PARTIAL

Commit Message

Check Status Note

Subject matches upstream ⚠️ Cannot verify - upstream series not accessible on lore

Body preserves rationale ✅ Clear technical descriptions present in all commits

Fixes tag present/correct N/A Not a fix; new feature addition

Authorship preserved ✅ Akhil P Oommen as author on all commits

Backport note (if applicable) N/A FROMLIST prefix indicates pending upstream, not backport

Diff

File Status Notes

drivers/gpu/drm/msm/adreno/a6xx_gpu.h ✅ Adds CLX data structures

drivers/gpu/drm/msm/adreno/a6xx_hfi.c ✅ Implements HFI CLX/IFF/PCLX support functions

drivers/gpu/drm/msm/adreno/a6xx_catalog.c (commit 2) ✅ Adds A840 CLX tables

drivers/gpu/drm/msm/adreno/a6xx_catalog.c (commit 3) ✅ Adds X2-85 CLX tables

Issues

Commit 2/3: Critical typo in Link tag

Line contains Limit : instead of Link:

This breaks automated tooling that parses commit trailers

The space before the colon is also non-standard

Commit 2/3: Missing Link tag

Commits 1/3 and 3/3 have proper Link: tags

Commit 2/3 has the typo Limit : which should be Link:

Inconsistent with the other commits in the series

Sign-off chain

All commits follow proper DCO sign-off order: Author → Reviewer → Integrator ✅

Shivam Rawat's sign-off indicates integration into downstream tree ✅

Verdict

Do not merge as-is. Commit 2/3 has a critical typo (Limit : → Link:) that must be fixed before merging. The typo breaks commit message parsing and violates kernel commit message conventions.

Final Summary

Lore link present: Partial — commits 1/3 and 3/3 have proper Link: tags; commit 2/3 has typo Limit : instead of Link:

Lore link matches PR commits: Cannot verify — the lore series (dated 2026-05-16) is not accessible via curl/b4; either the archive hasn't propagated yet or the date is incorrect. All three commits reference the same series cover letter URL.

Upstream patch status: In review — FROMLIST prefix indicates patches posted to mailing list but not yet merged into mainline. Commits 2/3 and 3/3 have Reviewed-by tags from Konrad Dybcio, suggesting active review.

PR present in qcom-next: Not checked — per constraints, no kernel tree access to verify integration status.

qlijarvis · 2026-06-29T18:53:30Z

PR #1434 — checker-log-analyzer

PR: #1434
Checker run: https://github.com/qualcomm-linux/kernel-config/actions/runs/28392828070

Checker	Result	Summary
Checker	Result	Summary
checkpatch	⚠️	1 warning in commit `419f5bd` (line length in commit message)
dt-binding-check	✅	No DT binding changes
dtb-check	✅	No devicetree changes
sparse-check	✅	Passed
check-uapi-headers	✅	No UAPI header changes
check-patch-compliance	❌	BLOCKER: Invalid Link tags and missing Link in commit 2/3
tag-check	N/A	Not applicable (no qcom-next branch)
qcom-next-check	✅	All commits properly tagged with FROMLIST:

Detailed report: Full report

Checker analysis — click to expand

🤖 CI Checker Analysis (checker-log-analyzer)

PR: #1434 - drm/msm: Add CLX feature support for A8x GPUs
Source: https://github.com/qualcomm-linux/kernel-config/actions/runs/28392828070

Checker Result Summary

checkpatch ⚠️ 1 warning in commit 419f5bd (line length in commit message)

dt-binding-check ✅ No DT binding changes

dtb-check ✅ No devicetree changes

sparse-check ✅ Passed

check-uapi-headers ✅ No UAPI header changes

check-patch-compliance ❌ BLOCKER: Invalid Link tags and missing Link in commit 2/3

tag-check N/A Not applicable (no qcom-next branch)

qcom-next-check ✅ All commits properly tagged with FROMLIST:

❌ check-patch-compliance

Root cause: Invalid Link tags pointing to series cover letter instead of individual patches, and missing Link tag in commit 2/3.

Failure details:
Checking commit: FROMLIST: drm/msm/a6xx: Add HFI support for CLX feature
Something seems wrong with the provided link. Please verify it
Try below command to run locally-
b4 am --single-message -C -l -3 https://lore.kernel.org/all/20260516-a8xx-clx-support-v1-0-62508bf651ac@oss.qualcomm.com/

Checking commit: FROMLIST: drm/msm/a6xx: Enable CLX feature on A840
No 'Link' found in commit message

Checking commit: FROMLIST: drm/msm/a8xx: Enable CLX feature on Adreno X2-85
Something seems wrong with the provided link. Please verify it
Try below command to run locally-
b4 am --single-message -C -l -3 https://lore.kernel.org/all/20260516-a8xx-clx-support-v1-0-62508bf651ac@oss.qualcomm.com/
Analysis:

Commit 1/3: Link tag points to the series cover letter (20260516-a8xx-clx-support-v1-0-62508bf651ac@oss.qualcomm.com) instead of the individual patch message-ID

Commit 2/3: Has Limit : instead of Link: (typo in tag name), making it unrecognized

Commit 3/3: Same issue as commit 1/3 - points to cover letter instead of individual patch

Fix:

For FROMLIST patches, each commit must have a Link: tag pointing to the individual patch on lore.kernel.org, not the series cover letter.

Steps to fix:

Find the correct message-IDs for each individual patch in the series on lore.kernel.org

Update commit 1/3 to use the correct Link for patch 1/3

Fix commit 2/3: Change Limit : to Link: and use the correct message-ID for patch 2/3

Update commit 3/3 to use the correct Link for patch 3/3

The Link format should be:
Link: https://lore.kernel.org/all/<individual-patch-message-id>@oss.qualcomm.com/
Reproduce locally:
cd /path/to/kernel
git log --format=fuller HEAD~3..HEAD
# Verify each commit has a valid Link: tag pointing to individual patches

# Test with b4 (should succeed for each individual patch):
b4 am --single-message -C -l -3 <link-from-commit-message>
⚠️ checkpatch

Root cause: Line length exceeds 75 characters in commit message of commit 2/3.

Failure details:
WARNING: Prefer a maximum 75 chars per line (possible unwrapped commit description?)
#10: 
Limit : https://lore.kernel.org/all/20260516-a8xx-clx-support-v1-0-62508bf651ac@oss.qualcomm.com/

419f5bd3a688d0dc97e178cb4e92034dea26da2a total: 0 errors, 1 warnings, 0 checks, 98 lines checked
Fix: This warning will be automatically resolved when fixing the check-patch-compliance issue above, as the Limit : line will be changed to Link: (which is the correct tag name). The line length warning is a side effect of the malformed tag.

Reproduce locally:
./scripts/checkpatch.pl --strict --git HEAD~3..HEAD
Verdict

2 blockers must be fixed before merge:

check-patch-compliance (BLOCKER): All three commits have incorrect or missing Link tags. Each FROMLIST commit must have a valid Link: tag pointing to the individual patch message-ID on lore.kernel.org, not the series cover letter.

checkpatch (minor): Commit 2/3 has a line length warning, but this is caused by the malformed Limit : tag and will be resolved when fixing issue For pinctrl #1.

Action required: Update all three commits with correct Link: tags pointing to individual patch message-IDs from the lore.kernel.org series.

akhilpo-qcom and others added 11 commits May 14, 2026 18:03

qcomlnxci requested review from a team and Rajesh Kemisetti (quic-rajeshk) and removed request for a team June 29, 2026 18:01

Shivam Rawat (shivrawa) force-pushed the tech/mm/gpu branch from e72c663 to 8e0a454 Compare June 29, 2026 18:03

qcomlnxci requested a review from a team June 29, 2026 18:05

akhilpo-qcom added 2 commits June 29, 2026 23:35

Shivam Rawat (shivrawa) force-pushed the tech/mm/gpu branch from 8e0a454 to fd5984c Compare June 29, 2026 18:06

Rajesh Kemisetti (quic-rajeshk) force-pushed the tech/mm/gpu branch from a124445 to 4433b06 Compare July 2, 2026 17:26

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Tech/mm/gpu : Enable CLX support#1434

Tech/mm/gpu : Enable CLX support#1434
Shivam Rawat (shivrawa) wants to merge 14 commits into
qualcomm-linux:tech/mm/gpufrom
shivrawa:tech/mm/gpu

Shivam Rawat (shivrawa) commented Jun 29, 2026

Uh oh!

qlijarvis commented Jun 29, 2026

🔍 Patch Validation

Commit Message

Diff

Issues

Verdict

Final Summary

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qlijarvis commented Jun 29, 2026

🤖 CI Checker Analysis (checker-log-analyzer)

❌ check-patch-compliance

⚠️ checkpatch

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Shivam Rawat (shivrawa) commented Jun 29, 2026

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qlijarvis commented Jun 29, 2026

PR #1434 — validate-patch

Final Summary

🔍 Patch Validation

Commit Message

Diff

Issues

Verdict

Final Summary

Uh oh!

qlijarvis commented Jun 29, 2026

PR #1434 — checker-log-analyzer

🤖 CI Checker Analysis (checker-log-analyzer)

❌ check-patch-compliance

⚠️ checkpatch

Verdict

Uh oh!

Reviewers

Assignees

Labels

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Development

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3 participants