Add riscv half-precision floating point detection

[ken-unger]

Add cpuinfo_has_riscv_zfh() and cpuinfo_has_riscv_zvfh for fp16 detection.

The motivation here is to enable this runtime detection support in xnnpack for its rvv fp16 kernels. (xnnpack uses this library)

[fbarchard]

LG. can you confirm this is vector arithmetics and is there a different detect for conversion?
another isa that would be great to detect is the 8 bit dot product

[ken-unger]

Thanks. zfh is scalar while zvfh is vector arithmetics, and both include the respective conversion instructions. Platforms only supporting conversion, without arithmetics, include the minimal subset isa zfhmin and zvfhmin respectively. My exposure is limited to sifive x280 and spacemit x60 (bpi-f3) which both support the full zfh/zvfh isa. However, for other (unknown) platforms we could add a cpuinfo_has_riscv_zfhmin() and cpuinfo_has_riscv_zvfhmin() in a future PR. model name : Spacemit(R) X60 isa : rv64imafdcv_zicbom_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zfhmin_zca_zcd_zba_zbb_zbc_zbs_zkt_zve32f_zve32x_zve64d_zve64f_zve64x_zvfh_zvfhmin_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt The 8 bit dot product would indeed be great to detect and expose, but that standard is not yet ratified. There is a sifive x280 proprietary extension Xsfvqmaccqoq (Int8 Matrix Multiplication Instructions - 4x8x4) which I may look to add in future, and which is currently exposed in hwprobe. ( https://docs.kernel.org/arch/riscv/hwprobe.html).

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On Wed, Mar 4, 2026 at 1:24 AM fbarchard ***@***.***> wrote: ***@***.**** approved this pull request. LG. can you confirm this is vector arithmetics and is there a different detect for conversion? another isa that would be great to detect is the 8 bit dot product — Reply to this email directly, view it on GitHub <#375 (review)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AZ2FOVOCPFGU2N474HK5ATD4O7Y4FAVCNFSM6AAAAACWF65DZGVHI2DSMVQWIX3LMV43YUDVNRWFEZLROVSXG5CSMV3GSZLXHMZTQOBYGE3DONJRHE> . You are receiving this because you authored the thread.Message ID: ***@***.***>

[fbarchard]

Perfect. For XNNPack running on SiFive X280 its supposed to have zfh/zvfh, but the qemu I use doesnt support fp16, and cpuinfo didnt detect them.
x280 also has int8 dotproduct .. eg.
vqdot.[vv,vx]
Both would be useful for writing good microkernels for xnnpack. Its not clear its worth supporting zvfhmin - thats for lower end cpus like SiFive P650

[ken-unger]

Is there a maintainer who could review and merge (if accepted) this PR? Thank you.

[fbarchard]

As we are waiting on this to land, and then roll into XNNPack, I've added similar code in hardware-config.c for XNNPack.
google/XNNPACK#9892

It should be removed in favor of cpuinfo when possible.

[malfet]

@pytorchbot rebase