test(vcr-oracle): pin #518 cross-backend contrast — RV32 loud-skips vs ARM silent miscompile (#242)#528
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…ps, ARM silently miscompiles (#242, #518) No new external signal this issue-hunt pass (gates #418/#472/#396-emitter still await external triggers; no new issues/comments since watermark; deps unchanged). Bounded behavior-frozen #242 increment, cross-backend parity (VCR-SEL-005): measure how the #518 i64-param root cause manifests on RISC-V. Measured (objdump symtab + compile stderr): the SAME root cause (an i64 param is never classified i64, so it reaches an i64 op as an i32 operand) is SILENT on ARM (#518 miscompile) but LOUD-SKIPPED on RV32. The RV32 selector validates the operand-stack TYPE before lowering an i64 op, hits `stack type mismatch ... expected i64, found i32`, returns a typed Err → `warning: skipping function …` + absent symbol. That is the #378/#180/#185 never-guess Ok-or-Err contract acting as the honest-fail backstop ARM's select_with_stack LACKS for i64 params. So on this class RV32 is INCOMPLETE-but-SOUND; ARM is COMPLETE-but-UNSOUND until the gated fix. - scripts/repro/i64_param_518_riscv_loudskip.py: asserts all 7 i64-param fns are loud-skipped (warning + absent symbol) AND the i32 control (t_i32) is emitted (non-vacuity — the skip is #518-specific, not a blanket backend failure). A regression removing the RV32 stack-type guard would flip a loud-skip into a silent miscompile, which the oracle catches. - roadmap VCR-ORACLE-001 #518 entry: record the cross-backend contrast. FROZEN-SAFE — no codegen touched (frozen anchors 3/3 green); rivet clean. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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What
Issue-hunt pass with no new external signal (gates #418/#472/#396-emitter still await external triggers; no new issues/comments since the watermark; deps unchanged). Bounded behavior-frozen #242 increment serving cross-backend parity (VCR-SEL-005): measure how the #518 i64-param root cause manifests on RISC-V.
Measured — same root cause, opposite manifestation
objdumpsymtab + compile stderr: the same omission (an i64 param is never classified i64, so it reaches an i64 op as an i32 operand) is silent on ARM (#518 miscompile) but loud-skipped on RV32. The RV32 selector validates the operand-stack type before lowering an i64 op →stack type mismatch ... expected i64, found i32→ typedErr→warning: skipping function …+ absent symbol. That is the #378/#180/#185 never-guess Ok-or-Err contract acting as the honest-fail backstop ARM'sselect_with_stacklacks for i64 params.So on this class RV32 is incomplete-but-sound (no silent wrong-code); ARM is complete-but-unsound until its gated fix — the precise VCR-SEL-005 parity shape (ARM lowers X; RV32 loud-declines X).
Changes (frozen-safe — no codegen touched; frozen anchors 3/3 green)
scripts/repro/i64_param_518_riscv_loudskip.py: asserts all 7 i64-param fns are loud-skipped (warning + absent symbol) and the i32 control (t_i32) is emitted (non-vacuity — the skip is arm: i64 binop with an i64 param silently miscompiles — param read from wrong registers (both paths) #518-specific, not a blanket backend failure). A regression removing the RV32 stack-type guard would flip a loud-skip into a silent miscompile, which this oracle catches.VCR-ORACLE-001arm: i64 binop with an i64 param silently miscompiles — param read from wrong registers (both paths) #518 entry: record the cross-backend contrast.rivet clean. The byte-changing fix stays a separate gated step.
Refs #242, #518.
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