test(vcr-oracle): broaden #518 oracle to the full AAPCS i64-param matrix (#242)#526
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…rix (#242, #518) No new external signal this issue-hunt pass (gates #418/#472/#396-emitter still await external triggers; no new issues/comments since watermark; deps unchanged). Bounded behavior-frozen #242 increment: harden the #518 characterization oracle (landed #525) to cover the AAPCS register-assignment cases the gated fix's mapping logic must handle but the single-param fixture missed. Measured (objdump force-thumb + unicorn vs wasmtime) — distinct failure modes the sequential `index_to_reg(i)` param mapping produces beyond the single-param clobber: - (i64,i64): p1 is the even-aligned pair R2:R3 but sequential mapping puts it at R1, so `i64.add(p0,p1)` emits `adds r3,r0,r1` = p0.lo+p0.hi (not p0+p1). - (i64,i32): the trailing i32 param (R2) is ignored entirely. - reading only the SECOND i64 param: sequential reads p1 from R1 (wrong) AND the i64.const clobbers R2 (the real p1.lo). Fixture grows by t_ii_add / t_i64_i32 / t_snd_i64; the differential gains those cases (AAPCS-correct arg placement already handles even-aligned pairs) and an explicit i32-control-regression guard (a broken control now FAILS the characterization rather than being masked by the divergence count). Result: 10/10 i64-param functions diverge on BOTH paths; i32 control correct on both. FROZEN-SAFE — no codegen touched (frozen anchors 3/3 green); rivet clean. The byte-changing fix stays a separate gated step. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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What
Issue-hunt pass with no new external signal (gates #418/#472/#396-emitter still await external triggers; no new issues/comments since the watermark; deps unchanged). Bounded behavior-frozen #242 increment: harden the #518 characterization oracle (landed #525) to cover the AAPCS register-assignment cases the gated fix's mapping logic must handle but the single-param fixture missed.
Measured — distinct failure modes beyond the single-param clobber
objdump -M force-thumb+ unicorn vs wasmtime, on the sequentialindex_to_reg(i)param mapping:(i64,i64): p1 is the even-aligned pair R2:R3 but sequential mapping puts it at R1, soi64.add(p0,p1)emitsadds r3,r0,r1= p0.lo+p0.hi (not p0+p1).(i64,i32): the trailing i32 param (R2) is ignored entirely.i64.constclobbers R2 (the real p1.lo).Changes (frozen-safe — no codegen touched; frozen anchors 3/3 green)
i64_param_518.wat: +t_ii_add/t_i64_i32/t_snd_i64.i64_param_518_differential.py: + those cases (AAPCS-correct arg placement already handles even-aligned pairs) and an explicit i32-control-regression guard (a broken control now fails the characterization rather than being masked by the divergence count). Result: 10/10 i64-param fns diverge on both paths; i32 control correct on both.VCR-ORACLE-001arm: i64 binop with an i64 param silently miscompiles — param read from wrong registers (both paths) #518 entry: note the full single/dual/even-aligned matrix coverage.rivet clean. The byte-changing fix stays a separate gated step.
Refs #242, #518.
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