docs(vcr): correct #503 falcon result — gale-verified 0 of 3, not 2 of 3 (#503, #242)

[avrabe]

What

Corrects a falsified prediction in the VCR-RA-001 roadmap. It recorded that the
v0.16.0 >8-scalar AAPCS stack-arg fix (#504) unblocked "2 of 3 (func_57/58)"
falcon helpers. gale's silicon verification (v0.16.0 @ 4a6b1ef, 2026-06-26)
falsified it: 0 of 3 — all three carry i64, so lifting the >8-scalar cap only
exposed their true blocker (the "10/25 params" labels were the scalar check
tripping first and masking the i64 signature).

Brings the trace to the verified facts:

• arm: functions needing the AAPCS stack-arg path (>8 scalar params, or any 64-bit stack param) are skipped, not lowered #503 stays OPEN for the 64-bit-stack-param sub-case (func_57/func_163);
  only the >8-scalar sub-case shipped in v0.16.0.
• func_58 is a distinct wall — i64-register-pair allocation (no high reg for
  the R8 pair), Epic: verified-codegen infrastructure (VCR-*) — replace the patch-accreting selector + allocator #242/regalloc territory, not the stack-arg path.
• falcon skip count 29/145 unchanged until both pieces land; jess v0.6.0
  correctly lists arm: functions needing the AAPCS stack-arg path (>8 scalar params, or any 64-bit stack param) are skipped, not lowered #503 as an open v0.7.0 supplier pole.

Why

Prevents the "gate-surprise" anti-pattern: the loop (and my own task tracking) had
treated #503 as fully resolved, when its i64 half is the actual falcon blocker.
Surfaced by this pass's dependency-release triage (jess v0.6.0 naming #503 a pole).

Gate

Behavior-frozen — docs/traceability only, no code/.text change. YAML valid; rivet
validate 0 non-xref errors.

🤖 Generated with Claude Code

[codecov]

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