Change GAP9 L3 dma to Async

[runwangdl]

Switch the GAP9 L3 (HyperRAM) DMA from the blocking adapter to the native asynchronous GAP9L3Dma, so the L3↔L2 hop overlaps with cluster compute under double-buffering instead of stalling on every tile transfer.

AnydimAsyncDmaTransferAdapter decomposes a rank-N transfer into a loop of rank-K
sub-transfers, and reuses one per-tensor Future — i.e. one pi_cl_ram_req_t struct
— across every iteration:
pi_cl_ram_req_t tensor_input = {0}; // one struct, shared by all iterations

  for (int i = 0; i < N; i++) {
      void*    dst_i = local    + i * loc_stride;
      uint32_t src_i = external + i * ext_stride;
      pi_cl_ram_copy_2d(get_ram_ptr(),
                        src_i, dst_i, size, stride, length, ext2loc,
                        &tensor_input);       // fires async, returns immediately
  }
  pi_cl_ram_copy_wait(&tensor_input);         // one wait after the whole loop

The src / dst / size / stride / length arguments do differ per iteration, but
pi_cl_ram_req_t is not a passive argument container. PMSIS uses it as the
driver's own queue node:

  struct pi_cl_ram_req_s {
      void            *addr;         // transfer params
      uint32_t         pi_ram_addr;  //   (overwritten by every pi_cl_ram_copy_2d)
      uint32_t         size;
      int32_t          stride;
      uint32_t         length;
      pi_evt_t         event;        // driver-owned completion event
      struct pi_cl_ram_req_s *next;  // driver's linked-list link
      uint8_t          done;         // driver-owned completion flag
      // ...
  };

Every pi_cl_ram_copy_2d(&req, …) (a) stamps the parameter fields into the struct,
(b) links req->next = queue_head; queue_head = &req, so the user-owned struct
becomes part of the driver's request queue, then (c) programs µDMA and returns.

When iter-1 fires while iter-0 is still in flight, three things break at once on
the same memory:

• iter-0's addr / pi_ram_addr / size / stride / length are overwritten with
  iter-1's values → the pending µDMA descriptor is corrupted;
• req->next = queue_head = &req → the driver's linked list becomes
  self-referential;
• done / event can only track one completion → the final pi_cl_ram_copy_wait
  can't distinguish which iteration finished.

Result: µDMA reads a garbled descriptor, the queue traversal wedges, and the
cluster hangs in pi_cl_ram_copy_wait — the hang observed on GAP9 CHW convs and
strided 2D ConvGrad L3 transfers.

Generated C:

  for (int i = 0; i < N; i++) {
      pi_cl_ram_copy_2d(..., &tensor_input);          // fire
      if (tensor_input.size != 0) {                   // ← inline wait
          pi_cl_ram_copy_wait(&tensor_input);
      }
  }

Added

• Tests/Kernels/FP32/Transpose3D regression test: a small-L1 NCHW→NHWC transpose whose L3 tile becomes a rank-3 transfer and exercises the Anydim decomposition path. Hangs without the fix, passes with it.
• GAP9 L3 double-buffer coverage: added the validated MLPerf (KeywordSpotting / ImageClassification / AnomalyDetection), Attention and Transformer networks to L3_DOUBLEBUFFER_MODELS.

Changed

• gap9L3DmaHack now uses the asynchronous GAP9L3Dma() directly instead of wrapping it in BlockingDmaFromAsyncDmaAdapter, so the L3 double-buffer hop overlaps transfers with compute.

Fixed

• AnydimAsyncDmaTransferAdapter.transfer: when a transfer is decomposed into a loop of lower-rank copies, wait for each sub-copy before issuing the next, so only one copy is ever in flight on the shared request handle. This prevents the async request-reuse overrun/hang on decomposed (rank > kernel-rank) transfers. Non-decomposed (rank-2) transfers are untouched and stay fully asynchronous, preserving the double-buffer overlap.
• Dropped the now-unused BlockingDmaFromAsyncDmaAdapter import in GAP9/DMA/L3Dma.py.

Trade-off: the decomposed rank-3 sub-copies are serialized, so those specific transfers don't overlap with compute. This affects only rank-3 (e.g. channels-first) L3 tiles, which no upstream network produces — every upstream GAP9/Siracusa network uses rank-2 L3 transfers and keeps full async overlap. If overlap is ever needed for the decomposed case, a per-sub-transfer request pool can be layered on top without changing this path.

PR Merge Checklist

1. The PR is rebased on the latest devel commit and pointing to devel.
2. Your PR reviewed and approved.
3. All checks are passing.
4. The CHANGELOG.md file has been updated.
5. If the docker was modified, change back its link after review.

[coderabbitai]

📝 Walkthrough

Walkthrough

gap9L3DmaHack now uses GAP9L3Dma() directly, and decomposed async DMA transfers now wait on the shared future after each sub-transfer. GAP9 tiled test config entries were extended for the affected models and kernels.

Changes

GAP9 DMA updates

Layer / File(s)	Summary
Direct GAP9 L3 DMA export Deeploy/Targets/GAP9/DMA/L3Dma.py	gap9L3DmaHack is assigned GAP9L3Dma() directly and the removed adapter import is dropped.
Wait after decomposed DMA issue Deeploy/TilingExtension/AsyncDma.py, DeeployTest/test_gap9_tiled_config.py	AnydimAsyncDmaTransferAdapter.transfer appends future.wait() in the decomposition path, and GAP9 tiled test config adds model and kernel entries for the updated async-L3 cases.

Estimated code review effort

🎯 2 (Simple) | ⏱️ ~10 minutes

Possibly related PRs

• pulp-platform/Deeploy#143: Overlaps the GAP9 L3 DMA export change by updating gap9L3DmaHack to use GAP9L3Dma() directly.

Suggested labels

Feature

Suggested reviewers

• Victor-Jung
• Xeratec

🚥 Pre-merge checks | ✅ 4 | ❌ 1

❌ Failed checks (1 warning)

Check name	Status	Explanation	Resolution
Docstring Coverage	⚠️ Warning	Docstring coverage is 0.00% which is insufficient. The required threshold is 80.00%.	Write docstrings for the functions missing them to satisfy the coverage threshold.

✅ Passed checks (4 passed)

Check name	Status	Explanation
Linked Issues check	✅ Passed	Check skipped because no linked issues were found for this pull request.
Out of Scope Changes check	✅ Passed	Check skipped because no linked issues were found for this pull request.
Title check	✅ Passed	The title clearly matches the main change: switching GAP9 L3 DMA to the async path.
Description check	✅ Passed	The description matches the changes, covering the async GAP9 L3 DMA switch, decomposed DMA wait fix, and added regression/test coverage.

✨ Finishing Touches

🧪 Generate unit tests (beta)

• Create PR with unit tests

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[Victor-Jung]

Thanks for the fix, I also suspect the mchan_transfer_t struct to be accessed by the mchan_transfer_push_2d or other runtime functions while being overwritten...

Is the change to AnydimAsyncDmaTransferAdapter only affecting L3 transfers or also L2 transfers?

[Victor-Jung]

This is not a model and should be moved into a L3_DOUBLEBUFFER_KERNELS category.