32 bit CPU is as per the RV32I RISC-V ISA specification and need to support the following instruction classes:
R-type, I-type, S-type, SB-type (implementation of U and UJ type will earn bonus marks).
Once the implementation is completed, you need to verify the design with suitable assembly program.
Once the CPU design is completed, you need to integrate with a direct mapped cache with victim cache feature.
Your design will be evaluated based on the following:
Functionality - all the instructions in the above classes should work Resource usage Performance : how fast your CPU can run? So pay special attention to delay paths. This is a single cycle design - so it is important to reduce the overall delay as much as possible. You need to submit a report that includes:
Design approach highlighting how control logic is derived.
Achieved performance level
Complete program (as a separate file) - this should be synthesizable.
