A small project to implement a JK flip‑flop using three different modelling styles in Verilog: behavioral, dataflow, and gate‑level. Simulated with Icarus Verilog and compared with a Proteus schematic.
-- !! UNDER CONSRTUCTION
| Test | J | K | Mode | Expected Q (after clock↑) |
|---|---|---|---|---|
| 1 | 0 | 0 | Hold | Q stays the same |
| 2 | 0 | 1 | Reset | Q = 0 |
| 3 | 1 | 0 | Set | Q = 1 |
| 4 | 1 | 1 | Toggle | Q toggles |
| 5 | 0 | 1 | Reset again | Q = 0 |
The clock toggles every 10 time units (positive edge triggered).
Behavoiral === Test 1: JK = 00 (Hold) === Time=0 | CLK=0 | J=0 | K=0 | Q=0 | QBAR=1 Time=10 | CLK=1 | J=0 | K=0 | Q=0 | QBAR=1
=== Test 2: JK = 01 (Reset) === Time=20 | CLK=0 | J=0 | K=1 | Q=0 | QBAR=1 Time=30 | CLK=1 | J=0 | K=1 | Q=0 | QBAR=1
=== Test 3: JK = 10 (Set) === Time=40 | CLK=0 | J=1 | K=0 | Q=0 | QBAR=1 Time=50 | CLK=1 | J=1 | K=0 | Q=1 | QBAR=0
=== Test 4: JK = 11 (Toggle) === Time=60 | CLK=0 | J=1 | K=1 | Q=1 | QBAR=0 Time=70 | CLK=1 | J=1 | K=1 | Q=0 | QBAR=1 Time=80 | CLK=0 | J=1 | K=1 | Q=0 | QBAR=1 Time=90 | CLK=1 | J=1 | K=1 | Q=1 | QBAR=0
=== Test 5: Return to Reset === Time=100 | CLK=0 | J=0 | K=1 | Q=1 | QBAR=0 Time=110 | CLK=1 | J=0 | K=1 | Q=0 | QBAR=1 jkflipflop_behave_TB.v:37: $finish called at 120 (1s) Time=120 | CLK=0 | J=0 | K=1 | Q=0 | QBAR=1
Data flow === Test 1: JK = 00 (Hold) === CLK =0|J=0 | K=0 | Q = 1 | Qbar = 0 CLK =1|J=0 | K=0 | Q = 1 | Qbar = 0
=== Test 3: JK = 01 (Reset) === CLK =0| J=0 | K=1 | Q = 1 | Qbar = 0 CLK =1| J=0 | K=1 | Q = 0 | Qbar = 1
=== Test 2: JK = 10 (Set) === CLK =0| J=1 | K=0 | Q = 0 | Qbar = 1 CLK =1| J=1 | K=0 | Q = 1 | Qbar = 0
=== Test 4: JK = 11 (Toggle) === CLK=0 | J=1 | K=1 | Q = 1 | Qbar = 0 CLK=1 | J=1 | K=1 | Q = 0 | Qbar = 1 CLK=0 | J=1 | K=1 | Q = 0 | Qbar = 1 CLK=1 | J=1 | K=1 | Q = 1 | Qbar = 0
=== Test 5: JK = 01 (RESET) === CLK=0 | J=0 | K=1 | Q = 1 | Qbar = 0 CLK=1 | J=0 | K=1 | Q = 0 | Qbar = 1
// gate level
=== Test 1: JK = 00 (Hold) === CLK =0|J=0 | K=0 | Q = 1 | Qbar = 0 CLK =1|J=0 | K=0 | Q = 1 | Qbar = 0
=== Test 3: JK = 01 (Reset) === CLK =0| J=0 | K=1 | Q = 1 | Qbar = 0 CLK =1| J=0 | K=1 | Q = 0 | Qbar = 1
=== Test 2: JK = 10 (Set) === CLK =0| J=1 | K=0 | Q = 0 | Qbar = 1 CLK =1| J=1 | K=0 | Q = 1 | Qbar = 0
=== Test 4: JK = 11 (Toggle) === CLK=0 | J=1 | K=1 | Q = 1 | Qbar = 0 CLK=1 | J=1 | K=1 | Q = 0 | Qbar = 1 CLK=0 | J=1 | K=1 | Q = 0 | Qbar = 1 CLK=1 | J=1 | K=1 | Q = 1 | Qbar = 0
=== Test 5: JK = 01 (RESET) === CLK=0 | J=0 | K=1 | Q = 1 | Qbar = 0 CLK=1 | J=0 | K=1 | Q = 0 | Qbar = 1 jkflipflop_gate_TB.v:103: $finish called at 450000 (1ps)
main challenge was the gate level due to constraints. Even with online resources it was proven as useless it was difficult. that is why a deep dive in the logic and real life scenario is required to succeed
There's something called an "unconnected" or "invalid" state. Imagine 1 as positive and 0 as negative but what if the battery terminal isn't connected to anything? It's not negative or positive; it's just floating.
- Unconnected / invalid states – a wire that’s not driven isn’t 0 or 1; it’s like a disconnected battery terminal.
- Race conditions – gate delays matter a lot.
- Initialisation – the flip‑flop might start unknown, so you have to force a reset.
EXPLANATION:
## you may also notice a late
## now as you observe it well that if J and K are 1 the clock transition from 1 --> 0 and 0 --> 1 repeatedly changes the Q by T flipflop logic
dataflow is just a quick delay command and follow how data follows each previous state so the invalid state will be just automatcially assigned to 0 then 1
while behaviorial is just following the characteristics which is the best one to use for flipflops
“kapoy away kopyha ni” – yes, this project was exhausting, especially the gate‑level part. But diving deep into the actual logic and debugging with real‑time prints made it all click. Recommended start with your simulation like protues If you’re struggling with gate‑level, just remember: it’s okay if it doesn’t work on the first or a hundredth try. Trace every wire, add prints, and when all else fails, open Proteus and stare at the waveforms until it makes sense.