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[NFC] Update Shader Flags section of DXIL.rst #7295

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Icohedron merged 11 commits into from
Jun 10, 2026
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[NFC] Update Shader Flags section of DXIL.rst #7295

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03d8c6a
Update Shader Flags documentation
Icohedron Apr 1, 2025
42ca0a3
Match feature info names in dxcdisassembler.cpp where it makes sense
Icohedron Apr 2, 2025
3421eb2
Correct Raster Ordered UAVs criteria. Correct Disable shader optimiza…
Icohedron Apr 2, 2025
aeca9eb
Fix wording for ROV flag criteria
Icohedron Apr 2, 2025
6fb8317
Update criteria for setting the m_bResMayNotAlias flag
Icohedron Apr 22, 2025
8030ce8
Correct the criteria used to set shader flag 16 (UAVs at every shader…
Icohedron Apr 22, 2025
cfe435b
Correct criteria used to set shader flag 15 (64 UAV slots)
Icohedron Apr 22, 2025
17ecebc
Update flag descriptions to match DXContainerConstants.def in LLVM
Icohedron Jun 10, 2025
297da7e
Merge remote-tracking branch 'origin/main' into dxil-rst-shader-flags
Icohedron Jun 10, 2026
5222f53
Revise shader flag descriptions based on PR feedback
Icohedron Jun 10, 2026
1ee2290
Double back-quote the characters for `~D3D10_SB_GLOBAL_FLAG_REFACTORI…
Icohedron Jun 10, 2026
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73 changes: 46 additions & 27 deletions docs/DXIL.rst
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Expand Up @@ -515,33 +515,52 @@ Additional shader properties are specified via tag-value pair list, which is the
Shader Flags
------------

Shaders have additional flags that covey their capabilities via tag-value pair with tag kDxilShaderFlagsTag (0), followed by an i64 bitmask integer. The bits have the following meaning:

=== =====================================================================
Bit Description
=== =====================================================================
0 Disable shader optimizations
1 Disable math refactoring
2 Shader uses doubles
3 Force early depth stencil
4 Enable raw and structured buffers
5 Shader uses min-precision, expressed as half and i16
6 Shader uses double extension intrinsics
7 Shader uses MSAD
8 All resources must be bound for the duration of shader execution
9 Enable view port and RT array index from any stage feeding rasterizer
10 Shader uses inner coverage
11 Shader uses stencil
12 Shader uses intrinsics that access tiled resources
13 Shader uses relaxed typed UAV load formats
14 Shader uses Level9 comparison filtering
15 Shader uses up to 64 UAVs
16 Shader uses UAVs
17 Shader uses CS4 raw and structured buffers
18 Shader uses Rasterizer Ordered Views
19 Shader uses wave intrinsics
20 Shader uses int64 instructions
=== =====================================================================
Shaders have additional flags that convey their capabilities via a tag-value pair with tag kDxilShaderFlagsTag (0), followed by an i64 bitmask integer. The bits have the following meaning, Shader Model requirements, and criteria for being set:

=== ==== ======================================================================================== ==========================================================================================================================================================================================================================================================================================================================================================
Bit SM Description Criteria to set shader flag
=== ==== ======================================================================================== ==========================================================================================================================================================================================================================================================================================================================================================
0 Disable shader optimizations Command-line flag ``/Od`` is provided to DXC
1 Disable math refactoring Only used in Dxilconv; corresponds to ``~D3D10_SB_GLOBAL_FLAG_REFACTORING_ALLOWED`` in DXBC
2 Double-precision floating point Use of the double data type
3 Force early depth-stencil test Shader is a pixel shader, and the ``[earlydepthstencil]`` attribute is present in the HLSL source
4 Raw and Structured buffers Use of RawBuffer or StructuredBuffer resource types
5 Low-precision data types present Use of half or i16 data types
6 Double-precision extensions for 11.1 Use of FDiv, UIToFP, SIToFP, FPToUI, FPToSI, or Fma instructions with a double type
7 Shader extensions for 11.1 Use of the Msad instruction
8 All resources bound for the duration of shader execution Command-line flag ``/all_resources_bound`` provided to DXC
9 SV_RenderTargetArrayIndex or SV_ViewportArrayIndex from any shader feeding rasterizer ViewPortArrayIndex or RenderTargetArrayIndex semantics are present in the input signature of a geometry shader, or the output signature of a vertex, domain, or hull shader
10 PS Inner Coverage Use of the InnerCoverage instruction, or the InnerCoverage semantic is present in the output signature of a pixel shader
11 PS Output Stencil Ref The StencilRef semantic is present in the output signature of a pixel shader
12 Tiled resources Use of the CheckAccessFullyMapped instruction, or the use of LodClamp in any of the instructions: SampleGrad, SampleCmpGrad, Sample, SampleBias, SampleCmp, or SampleCmpBias
13 Typed UAV load additional formats Use of TextureLoad or BufferLoad on a UAV with a multi-component data type.
14 Comparison filtering for feature level 9 Not set; unused legacy feature requirement flag
15 64 UAV slots More than 8 UAVs are declared, enabling the extended (64-slot) UAV register space. Each UAV array (range) contributes its range size to the count
16 UAVs at every shader stage This is set when a vertex, hull, domain, or geometry shader declares one or more UAVs
17 CS4 raw and structured buffers Use of RawBuffer or StructuedBuffer in a Shader Model 4.x compute shader
18 Raster Ordered UAVs Global presence of a rasterizer ordered view (ROV)
19 Wave level operations Use of any wave or quad intrinsic: WaveIsFirstLane, WaveGetLaneIndex, WaveGetLaneCount, WaveAnyTrue, WaveAllTrue, WaveActiveAllEqual, WaveActiveBallot, WaveReadLaneAt, WaveReadLaneFirst, WaveActiveOp, WaveActiveBit, WavePrefixOp, QuadReadLaneAt, QuadOp, WaveAllBitCount, WavePrefixBitCount, WaveMatch, WaveMultiPrefixOp, WaveMultiPrefixBitCount, QuadVote
20 64-Bit integers Use of i64 data types
21 6.1+ View Instancing Use of the ViewID instruction
22 6.1+ Barycentrics Use of the AttributeAtVertex instruction, or the Barcentrics semantic is present in the shader input signature
23 6.2+ Enable native low-precision data types Command-line flag ``-enable-16bit-types`` is provided to DXC
24 6.4+ ShadingRate The ShadingRate semantic is present in the shader input or output signature
25 6.5+ Raytracing tier 1.1 features Use of the AllocateRayQuery, AllocateRayQuery2, or GeometryIndex instruction

26 6.5+ Sampler feedback Use of any sampler feedback instructions: WriteSamplerFeedback, WriteSamplerFeedbackBias, WriteSamplerFeedbackLevel, and WriteSamplerFeedbackGrad
27 6.6+ 64-bit Atomics on Typed Resources Use of i64 AtomicBinOp or AtomicCompareExchange instructions on a typed resource
28 6.6+ 64-bit Atomics on Group Shared Use of i64 AtomicBinOp or AtomicCompareExchange instructions on group shared memory
29 6.6+ Derivatives in mesh and amplification shaders Use of instructions DerivFineX, DerivFineY, DerivCoarseX, DerivCoarseY, CalculateLOD, Sample, SampleBias, SampleCmp, or SampleCmpBias in a mesh or amplification shader
30 6.6+ Resource descriptor heap indexing Use of the CreateHandleFromHeap instruction on a resource descriptor heap
31 6.6+ Sampler descriptor heap indexing Use of the CreateHandleFromHeap instruction on a sampler descriptor heap
32 6.6+ 64-bit Atomics on Heap Resources Use of i64 AtomicBinOp or AtomicCompareExchange instructions on a descriptor heap resource
33 6.7+ Any UAV may not alias any other UAV Use of a UAV in any function, unless the ``-res-may-alias`` command-line flag is provided to DXC
34 6.7+ Advanced Texture Ops Use of SampleCmpLevel or TextureGatherRaw instructions, or the use of TextureLoad, SampleLevel, SampleCmpLevelZero, Sample Grad, SampleCmpGrad, Sample, SampleBias, SampleCamp, or SampleCmpBias with non-constant offsets
35 6.7+ Writeable MSAA Textures Set by use of the TextureStoreSample instruction or the presence of writeable MSAA texture resources accessed via a CreateHandle, CreateHandleForLib, or AnnotateHandle instruction
36 6.9+ Reserved Unused
37 6.8+ SampleCmp with gradient or bias Use of the instructions SampleCmpGrad or SampleCmpBias
38 6.8+ Extended command info Use of the instructions StartVertexLocation or StartInstanceLocation
=== ==== ======================================================================================== ==========================================================================================================================================================================================================================================================================================================================================================

Geometry Shader
---------------
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