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AXP2101: set the TS pin to external input on CoreS3 and Core2 v1.1 so it does not block the charger - #388
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… it does not block the charger TS has no battery thermistor on these boards; it senses the 5V bus (CoreS3) or reads about 2.9V (Core2 v1.1). REG 0x50 bit 4 selects whether TS qualifies charging, and its power-on default comes from the EFUSE and differs between chips: on units where it is 0, the charger treats the TS voltage as a cold battery and never charges (m5stack#387). Setting the bit is a no-op on chips whose default is already 1.
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Fixes #387.
On CoreS3 / CoreS3 SE / StackChan and Core2 v1.1 the AXP2101
TSpin has no battery thermistor: it senses the 5V bus (CoreS3) or reads about 2.9 V (Core2 v1.1). WhetherTSqualifies charging is selected byREG 0x50bit 4, and its power-on value comes from the EFUSE and differs between chips. On units where it is 0, the charger treats theTSvoltage as a cold battery (aboveVLTF-CHG) and never charges, as reported in #387 and on the forum.This sets
0x50[4]in the CoreS3-family and Core2 v1.1 initialization so thatTSis an external input that does not affect the charger. TheTSADC channel stays enabled, since the CoreS3 code uses it to detect 5V on the bus. The write is a no-op on chips whose default is already 1.Verification:
0x50= 0x1A) and Core2 v1.1 (0x50= 0x1F) here already had bit 4 set from the EFUSE; registers and charging state are unchanged with this patch.VLTF-CHGto 1.3 V and clearing bit 4: charging stopped immediately (0x01= 0x5D), and stayed stopped with bit 4 set again until VBUS was re-inserted.