DO NOT MERGE: just for testing#618
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This includes vendoring the debug module in and including it in the chip top. The CVA6 halt and exception addresses are fed in through the top and the debug module address is fed into the debug module. It also marks the license as Solderpad license for the Pulp debug module. Co-authored-by: Alexandre Joannou <alexandre@capabilitieslimited.co.uk> Co-authored-by: Jonathan Woodruff <jonathan.woodruff@capabilitieslimited.co.uk> Co-authored-by: Ray Lau <ray.lau@lowrisc.org> Co-authored-by: Marno van der Maas <mvdmaas+git@lowrisc.org>
The Verilator config allows program buffer access as fallback Disable GDB hardware breakpoints since these are not supported by the current CVA6 configuration and the trigger_module.sv doesn't work out of the box when enabled. This issue is tracked here: Capabilities-Limited/cheri-cva6#80 Co-authored-by: Marno van der Maas <mvdmaas+git@lowrisc.org>
With 2 hosts on the primary AXI crossbar, the device-side ID needs to be 1 bit ($clog2(AxiXbarHosts)) wider than the host-side ID. This commit adds device-side AXI types and improves comments about AXI ID widths in top_pkg.sv.
The debug module top now track pending resets and only acknowledges the reset when the core is ready to fetch again.
This is so the debug module knows when the CVA6 is ready to start fetching again.
This only works when SPI device is disconnected.
Before this you could not pass an SramInitFile into the core file.
This is necessary to have an example that doesn't actually exit the simulator.
This adds a shell script that launches Verilator, OpenOCD and GDB. GDB is run through an expect script.
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