Netlist - #675
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…al/instance naming routine names
Clarify comment Co-authored-by: Copilot Autofix powered by AI <175728472+Copilot@users.noreply.github.com>
This aligns central_naming with the simplified naming approach already adopted by all downstream branches (module_services, netlist, source_debug, systemc_trace, fst-writer). Changes: - Remove Namer._instanceNames cache field - Remove Namer.instanceNameOf(Module) method - Update synthesizers to use Namer.allocateName(String) directly - Remove destination tracking from _BusSubsetForStructSlice Benefit: Eliminates duplication across 5+ branches, making each branch truly orthogonal and mergeable without conflicts. Trade-off: Instance names no longer cached across synthesis passes, but all downstreams already use this simpler approach.
# Conflicts: # tool/gh_codespaces/install_dart.sh
instanceNameOf(Module) allocates a collision-free instance name on the first call and returns the cached result thereafter. The _instanceNames Map is keyed by Module.instanceNameKey so repeated synthesis passes over the same hierarchy always produce stable names. This method belongs in central_naming because it is pure naming infrastructure with no dependency on any feature branch.
- Update comment: 'allocateName' → 'instanceNameOf' - Add 'submodule instance names are stable across repeated definitions' test (the canonical 'run synthesis twice, same names' regression test) Both belong here since they directly exercise Namer.instanceNameOf, which is now defined in central_naming.
mkorbel1
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Aug 17, 2026
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can you pull main also again just so it's up to date?
Moved from Options to Configuration nomenclature. Dependency on rohd_hierarchy so we can use Occurrence classes Leverage Namer and eliminate residual naming functionality. Remove warnings and move to just throw on error.
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Pull request overview
Adds a Yosys-style JSON netlist synthesizer, shared synthesis utilities, hierarchy support, and a filter-bank example.
Changes:
- Introduces configurable netlist generation, validation, cell mapping, and optimization passes.
- Adds shared array/structure synthesis utilities and warning propagation.
- Adds extensive netlist tests and hierarchical filter-bank examples.
Reviewed changes
Copilot reviewed 41 out of 41 changed files in this pull request and generated 10 comments.
Show a summary per file
| File | Description |
|---|---|
test/synth_structure_layout_test.dart |
Tests packed structure layout. |
test/synth_name_parity_test.dart |
Tests naming parity across synthesizers. |
test/struct_port_pruning_test.dart |
Tests structured-port preservation. |
test/netlist_test.dart |
Tests netlist APIs and JSON output. |
test/netlist_example_test.dart |
Tests example netlist generation. |
pubspec.yaml |
Adds hierarchy dependency and publication settings. |
lib/src/synthesizers/utilities/utilities.dart |
Exports new synthesis utilities. |
lib/src/synthesizers/utilities/synth_structure_slice.dart |
Adds structure-slice helper. |
lib/src/synthesizers/utilities/synth_structure_layout.dart |
Adds structure layout mapping. |
lib/src/synthesizers/utilities/synth_structure_concat.dart |
Adds structure concatenation helper. |
lib/src/synthesizers/utilities/synth_module_stop_policy.dart |
Adds hierarchy stopping policies. |
lib/src/synthesizers/utilities/synth_logic.dart |
Adds nullable synthesized-name access. |
lib/src/synthesizers/utilities/synth_array_slice.dart |
Adds array-slice helper. |
lib/src/synthesizers/utilities/synth_array_concat.dart |
Adds array concatenation helper. |
lib/src/synthesizers/synthesizers.dart |
Exports netlist APIs. |
lib/src/synthesizers/synthesis_result.dart |
Adds synthesis warnings. |
lib/src/synthesizers/synth_builder.dart |
Aggregates result warnings. |
lib/src/synthesizers/netlist/netlist.dart |
Adds netlist barrel exports. |
lib/src/synthesizers/netlist/netlist_validation.dart |
Validates generated connectivity. |
lib/src/synthesizers/netlist/netlist_utils.dart |
Adds netlist translation utilities. |
lib/src/synthesizers/netlist/netlist_synthesizer.dart |
Implements JSON netlist synthesis. |
lib/src/synthesizers/netlist/netlist_synthesizer_configuration.dart |
Defines netlist options. |
lib/src/synthesizers/netlist/netlist_synthesis_result.dart |
Stores per-module netlists. |
lib/src/synthesizers/netlist/netlist_synth_module_definition.dart |
Preserves structural netlist cells. |
lib/src/synthesizers/netlist/netlist_passes.dart |
Adds optimization passes. |
lib/src/synthesizers/netlist/netlist_module_translation.dart |
Translates modules into netlist data. |
lib/src/synthesizers/netlist/netlist_cell_mapper.dart |
Maps ROHD modules to cells. |
lib/src/signals/const.dart |
Reformats constant construction. |
lib/src/module.dart |
Refactors constant detection. |
example/filter_bank/shared_data_bus.dart |
Adds bidirectional-bus example. |
example/filter_bank/mac_unit.dart |
Adds pipelined MAC example. |
example/filter_bank/filter_sample.dart |
Adds structured sample type. |
example/filter_bank/filter_data_interface.dart |
Adds filter interface. |
example/filter_bank/filter_controller.dart |
Adds filter FSM controller. |
example/filter_bank/filter_channel.dart |
Adds FIR channel implementation. |
example/filter_bank/filter_bank.dart |
Adds filter-bank top module. |
example/filter_bank/filter_bank_modules.dart |
Exports filter modules. |
example/filter_bank/coeff_bank.dart |
Adds coefficient storage. |
example/filter_bank.dart |
Adds simulation entry point. |
dart_test.yaml |
Configures benchmark timeout. |
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mkorbel1
reviewed
Aug 20, 2026
…ells, and using enum for port dirs
mkorbel1
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Aug 24, 2026
mkorbel1
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Aug 25, 2026
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naming change looks reasonable, but testing doesn't seem comprehensive. since the impact is just potentially the netlist, seems good enough for now to me. approved!
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Description & Motivation
This is a netlist synthesizer that produces a netlist for the generated design in an extension of the Yosys output netlist format.
It provides routines for emitting just the hierarchy and ports ("slim" mode) as well as fully expanded and has hooks for even more incremental expansion modes.
Related Issue(s)
None.
Testing
There is a suite of tests that compare the netlist and its names against the SystemVerilog output. This netlist depended on the last central_naming branch to assure that signals in both formats had identical names.
Backwards-compatibility
No.
Documentation
This is a minor API addition (
Module.generateNetlist()) but we will add more documentation and examples of the format, etc.It will have some options as well, such as multiFile, which should parallel the
generateSynth()API.