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[SYCL] PR 1 - Remove FPGA attributes from SYCL FE#21710

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premanandrao wants to merge 1 commit intointel:syclfrom
premanandrao:remote_fpga_pr1
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[SYCL] PR 1 - Remove FPGA attributes from SYCL FE#21710
premanandrao wants to merge 1 commit intointel:syclfrom
premanandrao:remote_fpga_pr1

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@premanandrao
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This removes the following attributes:

[[intel::loop_fuse]]
[[intel::loop_fuse_independent]]
[[intel::nofusion]]

This removes the following attributes:

[[intel::loop_fuse]]
[[intel::loop_fuse_independent]]
[[intel::nofusion]]
@premanandrao premanandrao requested a review from a team as a code owner April 9, 2026 00:38
@premanandrao
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#21102 requested that we split the large set of changes into manageable chunks. This is the first of many such chunks.

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The clang-formatter is pointing out changes that I did not make in this PR, so ignoring that fail.
(Code reviewers, please let me know if you do want me to make those changes as part of this PR.)

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Thanks @Fznamznon!

@intel/llvm-gatekeepers, this is ready for merge despite the clang-format test failure.

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