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JIT: Fix managed return value debug info for floating-point returns #129321

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JIT: Fix managed return value debug info for floating-point returns #129321

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f961152
JIT: Fix managed return value debug info for floating-point returns
tommcdon Jun 11, 2026
708ceee
Fix VLT_REG_FP encoding for enregistered float/SIMD locals
tommcdon Jun 12, 2026
346d4db
Fix VLT_REG_FP encoding for FP parameters in psiBegProlog
tommcdon Jun 13, 2026
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9 changes: 7 additions & 2 deletions src/coreclr/jit/codegencommon.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1831,12 +1831,17 @@ void CodeGen::genEmitCallWithCurrentGC(EmitCallParams& params)
info.returnValueLoc.vlType = VLT_FPSTK;
info.returnValueLoc.vlFPstk.vlfReg = 0;
#else
info.returnValueLoc.storeVariableInRegisters(REG_FLOATRET, REG_NA);
// VLT_REG_FP uses a 0-based FP register index; the DBI adds the
// platform-specific XMM0/V0 base when converting to CorDebugRegister.
info.returnValueLoc.vlType = VLT_REG_FP;
info.returnValueLoc.vlReg.vlrReg = (regNumber)(REG_FLOATRET - REG_FP_FIRST);
#endif
Comment on lines +1834 to 1838
}
else if (varTypeUsesFloatReg(call))
{
info.returnValueLoc.storeVariableInRegisters(REG_FLOATRET, REG_NA);
// VLT_REG_FP uses a 0-based FP register index.
info.returnValueLoc.vlType = VLT_REG_FP;
info.returnValueLoc.vlReg.vlrReg = (regNumber)(REG_FLOATRET - REG_FP_FIRST);
}
else
{
Expand Down
5 changes: 4 additions & 1 deletion src/coreclr/jit/ee_il_dll.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -894,14 +894,17 @@ void Compiler::eeDispVar(ICorDebugInfo::NativeVarInfo* var)
{
case CodeGenInterface::VLT_REG:
case CodeGenInterface::VLT_REG_BYREF:
case CodeGenInterface::VLT_REG_FP:
printf("%s", getRegName(var->loc.vlReg.vlrReg));
if (var->loc.vlType == (ICorDebugInfo::VarLocType)CodeGenInterface::VLT_REG_BYREF)
{
printf(" byref");
}
break;

case CodeGenInterface::VLT_REG_FP:
printf("%s", getRegName((regNumber)(var->loc.vlReg.vlrReg + REG_FP_FIRST)));
break;

case CodeGenInterface::VLT_STK:
case CodeGenInterface::VLT_STK_BYREF:
if ((int)var->loc.vlStk.vlsBaseReg != (int)ICorDebugInfo::REGNUM_AMBIENT_SP)
Expand Down
37 changes: 27 additions & 10 deletions src/coreclr/jit/scopeinfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -158,6 +158,9 @@ bool CodeGenInterface::siVarLoc::vlIsOnStack() const
//
void CodeGenInterface::siVarLoc::storeVariableInRegisters(regNumber reg, regNumber otherReg)
{
assert(genIsValidIntReg(reg));
assert(otherReg == REG_NA || genIsValidIntReg(otherReg));

if (otherReg == REG_NA)
{
// Only one register is used
Expand Down Expand Up @@ -409,10 +412,10 @@ void CodeGenInterface::siVarLoc::siFillRegisterVarLoc(
#ifdef TARGET_64BIT
case TYP_FLOAT:
case TYP_DOUBLE:
// TODO-AMD64-Bug: ndp\clr\src\inc\corinfo.h has a definition of RegNum that only goes up to R15,
// so no XMM registers can get debug information.
// VLT_REG_FP uses a 0-based FP register index; the DBI adds the
// platform-specific XMM0/V0 base when converting to CorDebugRegister.
this->vlType = VLT_REG_FP;
this->vlReg.vlrReg = varDsc->GetRegNum();
this->vlReg.vlrReg = (regNumber)(varDsc->GetRegNum() - REG_FP_FIRST);
Comment on lines +415 to +418
break;

#else // !TARGET_64BIT
Expand Down Expand Up @@ -442,12 +445,9 @@ void CodeGenInterface::siVarLoc::siFillRegisterVarLoc(
{
this->vlType = VLT_REG_FP;

// TODO-AMD64-Bug: ndp\clr\src\inc\corinfo.h has a definition of RegNum that only goes up to R15,
// so no XMM registers can get debug information.
//
// Note: Need to initialize vlrReg field, otherwise during jit dump hitting an assert
// in eeDispVar() --> getRegName() that regNumber is valid.
this->vlReg.vlrReg = varDsc->GetRegNum();
// VLT_REG_FP uses a 0-based FP register index; the DBI adds the
// platform-specific XMM0/V0 base when converting to CorDebugRegister.
this->vlReg.vlrReg = (regNumber)(varDsc->GetRegNum() - REG_FP_FIRST);
break;
}
#endif // FEATURE_SIMD
Expand Down Expand Up @@ -1736,7 +1736,24 @@ void CodeGen::psiBegProlog()

if (reg1 != REG_NA)
{
varLocation.storeVariableInRegisters(reg1, reg2);
if (genIsValidFloatReg(reg1))
{
// FP parameter in XMM/V register — encode as VLT_REG_FP with
// 0-based FP register index.
varLocation.vlType = VLT_REG_FP;
varLocation.vlReg.vlrReg = (regNumber)(reg1 - REG_FP_FIRST);
}
else
{
// Integer register parameter. On SysV x64, the second segment
// may be in an XMM register for mixed struct passing — drop it
// since VLT_REG_REG cannot encode FP registers.
if (reg2 != REG_NA && !genIsValidIntReg(reg2))
{
reg2 = REG_NA;
}
varLocation.storeVariableInRegisters(reg1, reg2);
}
}
else
{
Expand Down
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