Milestones
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Sequence optional product improvements only after dependable lap timing is proven. Exit gate: Each candidate has measured value, safety/privacy constraints, and a bounded design that cannot destabilize the core offline timer.
No due date•0/6 issues closedValidate performance and timing in progressively realistic conditions, then ship reproducible release artefacts. Exit gate: The documented 1.0 hardware and firmware pass soak, fault, multi-circuit timing, install, and release gates with no critical defects.
No due date•0/6 issues closedTurn the bench prototype into a mechanically and electrically robust dashboard-mounted unit. Exit gate: The assembled prototype survives measured power, thermal, vibration, connector, and handling tests without reset, data corruption, or loose hardware.
No due date•0/6 issues closedMake every accepted/rejected fix and timing decision durable, inspectable, and reproducible. Exit gate: The embedded result can be reproduced from stored traces, and SD latency or failure never stops active timing.
No due date•2/7 issues closedLoad safe, versioned, locally stored track geometry and support controlled track creation without rebuilding firmware. Exit gate: A new track can be validated, selected, loaded, hashed, and safely captured without rebuilding firmware.
No due date•8/11 issues closedBuild a host-verified timing engine and run the same deterministic behavior live on the ESP32-S3. Exit gate: Synthetic and recorded traces produce exactly one correctly directed event per valid crossing, and embedded/replay timestamps agree within a defined tolerance.
No due date•7/8 issues closedReceive, validate, configure, and diagnose a sustained 20/25 Hz u-blox NEO-M9N stream. Exit gate: A 30-minute outdoor 20 Hz log has the expected cadence, measurement timestamps, quality data, and no unexplained serial loss; 25 Hz is evaluated separately.
No due date•1/6 issues closedProve the selected Waveshare board and every onboard peripheral required by the product. Exit gate: A hardware diagnostic build exercises display, touch, IMU, RTC, storage, brightness, and power information for 30 minutes without reset.
No due date•1/11 issues closedMake a clean clone buildable, testable, and ready for disciplined collaborative development. Exit gate: A clean clone passes host checks and produces the ESP32-S3 bootstrap firmware using a documented, pinned toolchain.
No due date•7/14 issues closed