I design hardware that survives verification, and verify hardware that deserves tapeout.

I work at the intersection of RTL microarchitecture, protocol correctness, and verification rigor — translating specifications into clean, synthesizable logic and proving it works under real constraints.

• Architect RTL blocks with clear microarchitecture & FSM discipline
• Write synthesizable, timing-aware RTL
• Build self-checking verification environments
• Validate protocol compliance, not just happy paths
• Debug failures using waveforms, assertions, and specs
• Document assumptions, trade-offs, and limitations

I care about why a design works, not just that it simulates.

• Verilog
• SystemVerilog
• VHDL
• UVM
• SystemVerilog Assertions (SVA)

• C
• Python
• Perl

• Siemens Questa / ModelSim
• Xilinx Vivado
• Intel Quartus
• Cadence Virtuoso

• UVM-based Testbenches
• Assertion-Based Verification
• Functional & Code Coverage
• Formal Verification (working knowledge)

Legend:
✅ Implemented & verified
⚠️ Partial / learning
📘 Architectural understanding

🔗 https://github.com/cp024s/100-days-of-RTL

A disciplined RTL engineering initiative focused on depth, not demos.

What this project demonstrates:

• incremental RTL complexity with architectural intent
• consistent coding style & naming discipline
• verification-first mindset
• documentation of design decisions, assumptions, and edge cases

This is practice for real IP development, not tutorial recycling.

• RTL is a liability unless verified properly
• Specs are meaningless unless interpreted precisely
• Coverage without intent is false confidence
• Debug skill matters more than tool familiarity

I don’t chase tools.
I chase correctness.

📧 spamsofcp@gmail.com

Open to:

• RTL Design roles · SoC / IP Development · ASIC / FPGA Verification · Serious hardware collaborations

If your team values clean design, strong verification, and engineers who think, we should talk.