Alpha: Fix implicit read/write details for some memory instructions

[atirna]

Your checklist for this pull request

• I've documented or updated the documentation of every API function and struct this PR changes.
• I've added tests that prove my fix is effective or that my feature works (if possible)

Detailed description

Alpha memory-format instructions inherit R28 from LLVM as a compiler scratch-register reservation, but the encoded instructions do not implicitly write R28. I removed that generated write metadata through the existing Alpha auto-sync patch path and updated the architecture-specific and common detail expectations for both endian modes.

Test plan

• cstest tests/details/alpha.yaml (2 test cases, 8 decoded instructions)
• cstest tests/details/cs_common_details.yaml (49 test cases, 334 decoded instructions)
• cstest tests/details (1,104 passed, 2 skipped, 2,554 decoded instructions)
• cstool -d alpha 0200bb27507abd23d0ffde2300005eb7
• cstool -d alphabe 27bb000223bd7a5023deffd0b75e0000

The CLI now reports only the architectural destination registers for the loads and no modified register for stq.

Closing issues

Closes #3027

[atirna]

Added the detail checks for both Alpha byte orders: $29/$30 writes and $26,$30 reads. cstest tests/details/cs_common_details.yaml passes with the updated metadata.

[Rot127]

Please rebase to fix the test

[atirna]

rebased onto latest next, picks up #3047 for the autosync lit pin. pushed, waiting on ci