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Optional ESP32-S3 TFT LCD and W5500: isolated buses, shared network stack and physical acceptance #19
Description
Parent production checklist: #2. Related current-hardware contracts: #6; contextual capability acceptance: #10.
This is the single optional-hardware backlog for TFT LCD and W5500 on the ESP32-S3. Current BoardPins.h contains reservations only. There is no implemented/accepted Ethernet driver, TFT driver, network-link result or physical display acceptance in this issue's initial state. Keep the integrated firmware and all existing AVR/matrix/update services; do not create a separate Ethernet or display firmware.
Source reservation baseline, not wiring acceptance
- Existing source reservation inspected in firmware/esp32s3/src/BoardPins.h: AVR UART1 TX GPIO17 -> AVR RXD, RX GPIO18 <- AVR TXD; matrix output GPIO4; dedicated AVR ISP FSPI/SPI2 MOSI11/MISO13/SCK12/reset-driver10.
- Existing optional W5500 HSPI/SPI3 reservation inspected: SCK5, MISO6, MOSI7, CS8, RESET9, INT14. This is not initialized hardware or an Ethernet implementation.
- Identify the exact ESP32-S3 DevKit/module/revision, flash/PSRAM package and schematic. Confirm board silkscreen TX/RX routing separately from configurable UART1 GPIO17/18. Do not infer GPIO38 versus GPIO48 onboard RGB.
- Identify the exact W5500 module, supply input/regulator requirements, 3.3 V I/O, interrupt/reset polarity, oscillator, magnetics and maximum reviewed SPI clock. ESP32-S3 GPIOs are not 5 V tolerant. Confirm common ground and power/current budget without back-powering either USB host.
- Identify TFT controller, resolution, supply/backlight current/driver, bus mode, touch controller and touch bus/IRQ. No TFT GPIO allocation is approved yet.
- Produce one reviewed combined pin table/diagram: protect AVR hardware UART and confirmed A4 DIO/A5 CLK, isolated ISP/reset circuit, matrix4, optional W5500 reservations, actual RGB pin, USB19/20, bridge UART43/44, boot straps and module flash/PSRAM exclusions. Any TFT shared-bus/control-pin proposal needs explicit conflict/voltage review first.
Ethernet architecture and coexistence
- Use the pinned ESP32 core's native ETH/lwIP W5500 integration (ETH_PHY_W5500/SPIClass support exists in the installed 3.3.12 header), not an independent EthernetClient socket stack that duplicates WiFiClient/HTTP/TLS behavior. Compile/source API support is not runtime proof.
- Create an explicitly owned HSPI/SPI3 instance for W5500. Keep AVR ISP on its existing private FSPI/SPI2 bus and closed electrical/polarity gate. AVR ISP has no ordinary chip-select; never put the AVR ISP wires onto the W5500 bus.
- Define bus lifecycle/reset/interrupt ownership and failure cleanup. If TFT later shares a reviewed non-ISP SPI bus, provide real transaction/mutex arbitration, per-device CS and timing tests; otherwise allocate a conflict-free bus strategy. Do not duplicate the 480-pixel effects engine.
- Integrate Ethernet link/DHCP/static-IP/DNS/hostname into the existing network owner and persistent configuration. Preserve valid saved static profiles when toggling DHCP and preserve absent secret fields. Define priority/failover for Ethernet, Wi-Fi client, AP and AP+client; expose configured versus observed link/address separately.
- Use the same authenticated versionless JSON API, WebSocket/server/client, MQTT/TLS, streaming, NTP, Telnet/shell, firmware download and self-OTA/remote AVR-update services across native network interfaces. No parallel route registry, credentials or updater state machine.
- Integrate mDNS/DNS-SD, SSDP and MNDP with interface-correct address/TTL/membership and stable board/application identity. Test Ethernet/Wi-Fi/AP coexistence, rename/reconnect and teardown; never advertise unavailable NetBIOS or invented services.
- Keep board/boot/endpoint-bound authority across interface changes. Discovery does not grant mutation ownership; no uncertain-command replay, double dispatch or false success after failover. Deduplicate only identical incidents while retaining distinct route/cause failures.
TFT and shared application integration
- Add feature/build guards and real driver/capability ACK before advertising TFT/touch or Ethernet controls. Physical device absence is unknown/unavailable, not an enabled placeholder.
- Reuse shared scene/settings/menu models, application branding, status RGB values and front-panel navigation. AVR still owns TM1637, buzzer and keys; optional TFT does not move those peripherals or replace the existing six AVR pages.
- Render actual connection/configuration/update progress/error/peer state with appropriate localization, fonts, focus and accessible navigation. Input actions use the same validated/confirmed owner paths; no UI draft is shown as applied state.
- Provide contextual configuration/readback across applicable API, CLI/TUI, Telnet, Web, native, Flutter and physical front-panel surfaces. Small displays may show summaries/editor entry points, but unsupported configuration must be explicit and tracked rather than silently omitted.
- Add firmware-safe bounds for framebuffers, SPI transfers, PSRAM/DMA compatibility, watchdog/yield and update/ISP contention. Measure output throughput; do not introduce a hidden low-FPS matrix cap.
Evidence before any production acceptance
- Source tests and pinned SDK builds for enabled/disabled combinations, preserving ESP8266 compatibility and AVR UART/busy/poll/buffered profiles; source-hash donor mappings and exact omitted/replaced code reasons.
- Live W5500 link unplug/replug, DHCP renewal, validated static addressing/DNS, reboot persistence, routing/failover, AP recovery and discovery from both PCs and Android.
- Live TFT orientation, pixels/backlight/touch, font/Persian rendering, navigation and fault/reconnect states on the exact module.
- Live concurrent 480-pixel effects/streaming + UART key/display/buzzer + Ethernet/Wi-Fi + ISP/OTA contention. Measure counters/timing; test authorization, aborted/bad-hash updates, power interruption and real readback/backups before claiming safe recovery.
- Publish source/build/package/device/physical/human acceptance separately and link evidence to PakarController complete production acceptance and donor parity #2. Do not close PakarController complete production acceptance and donor parity #2 or mark optional hardware operational from a pin reservation, SDK declaration, host fixture or screenshot.
Working design and acceptance split: docs/S3-STATUS-FRONTPANEL-INTEGRATION.md. No credentials or private network secrets belong in this issue.
Activity
atomicdeploy commentedon Oct 18, 2026
S3 continuation checkpoint8a3827a preserves the independent optional W5500 bus and adds no TFT placeholder driver. W5500 mapping remains GPIO5 SCK /6 MISO /7 MOSI /8 CS /9 RSTn /14 INTn, separate from AVR ISP10..13, UART17/18, matrix4 and optional LCD15/16. Existing native ETH/lwIP source, persisted DHCP/static configuration, route failover and shared API/WebSocket/OTA architecture have host/SDK evidence; the connected production profile does not allocate this optional SPI bus until explicitly enabled. Actual module wiring, link, local serving/discovery, Ethernet-only Internet fetch/OTA and recovery still require physical tests. TFT interface/controller/pin ownership remains backlog, not implemented or accepted. Keep this existing issue rather than create duplicate hardware backlogs.
atomicdeploy commentedon Oct 19, 2026
LAN source/runtime checkpoint43f6add (firmware20a242b) is published. Native ETH/lwIP W5500 remains on its separate HSPI/SPI3 bus5/6/7/8/9/14, with independent enable/DHCP/static/hostname and observed-link state, shared APIs/WS/TLS/updater, bounded LLDP TX/optionalRX and source fixtures. Fresh profiles leave Ethernet DISABLED, avoiding unwired optional GPIO drive. Existing active saved profiles migrate without silent disable. TFT still backlog.
Actual production Wi-Fi+AP board now responds to mDNS/DNS-SD, SSDP, MNDP and NBNS/NBSTAT. Windows nbtstat from both ASUS wired and wireless interfaces reports LEDBOARD<00> and the correct board MAC; exact wire diagnostics retained. This is NOT ESP Ethernet/LLDP physical acceptance. No router IGD descriptor responded to scoped multicast/unicast probes; default/admin-label credentials remain unresolved, and no router login, mapping or firewall mutation was performed.
Native/Web/Flutter Ethernet editors have peer-bound ACK/readback fixtures and built packages, not installed-client/hardware acceptance. Current matrix/DMA stack recovery and optical/NTP limitations are recorded under #2 and docs/ESP32-S3-COMMISSIONING.md. Actual W5500 wiring/link/unplug/static/DHCP/Ethernet-only fetch and same-route serving remain UNCHECKED until physical hardware confirmation. No optional-hardware acceptance boxes closed.
atomicdeploy commentedon Oct 28, 2026
SSDP board icons / UPnP description checkpoint — 2026-10-28
Source: 30fad46 in existing PR #27; related #10 and parent #2. No production acceptance checkbox is advanced.
Implemented:
/description.xmlnow advertises the matching table/key/generic PNG viaiconList, actual PNG width/height/depth and public GET/HEAD/board-icon.png.Verification:
Live limitations: read-only gateway SSDP/IGD probe received no gateway IGD response; that does not establish disabled vs unsupported. ASUS localhost:8022 still refused SSH. No board deployment/reboot/output/configuration, router login/mapping or firewall mutation occurred. Actual icon fetch/rendering, wire-level discovery/lifecycle and router interoperability remain open. Not UPnP conformance certification. Existing PR CI failure at pc_contract_mapping_test's AVR target hash is separate; this checkpoint does not claim full CI green.