[0z5a]

relax.median currently legalizes its sort to a CPU packed function even for GPU targets. A simple median therefore reaches CUDA code generation with tirx.call_packed in a device kernel and fails to compile.

Dispatch GPU median with a known input shape to the existing GPU argsort implementation, then select the lower middle value and, for an axis reduction, its original index. Global reductions retain the requested keepdims shape. The CPU and target-less paths remain unchanged; the new dispatch covers the existing global and single-axis cases.

Fixes #20673.

Testing

• Reproduced the unresolved packed-call error on the original CUDA path; the change compiles global and single-axis median.
• GH200 and B300: 9 GPU regression cases passed on each device, covering values, indices, scalar inputs, FP16, integer inputs, global and axis reductions, and symbolic row counts. The B300 test used a local CUDA header-layout view so NVRTC could find the toolkit's CCCL headers.
• NVPTX (sm_80): global and single-axis cases compiled; no NVPTX runtime test was run.
• Median and existing sort/scan dispatch tests with GPU visibility disabled: 34 passed, 28 skipped, 1 xpassed.
• Applicable changed-file pre-commit checks, including ASF headers and Ruff, passed; unrelated language-specific hooks were skipped.