Fix phantom exception 528 during Cortex-M tail-chaining/return

[PAException]

Fixes renode/renode#995

Description:
This PR fixes a bug in the ARM Cortex-M tlib emulation where exception returns from unaligned stacks could cause the emulator to complete a phantom, invalid exception (often HardwareIRQ#512).

The Issue:
During exception entry, if the stack is not 8-byte aligned, the Cortex-M hardware (and tlib) correctly sets bit 9 (0x200 = 512) in the stacked xPSR. However, during certain exception returns (such as tail-chaining into a PendSV context switch triggered by FreeRTOS's xQueueSendFromISR), tlib reads the returning exception number from the popped xPSR but fails to isolate the 9-bit IPSR field. The stack alignment bit (0x200) leaks into the env->v7m.exception variable, causing the emulator to pass a corrupted exception number (like 528) back to the C# NVIC.cs, which throws a Trying to complete not active IRQ error.

The Fix:
Updated helper.c to properly apply the 0x1ff bitmask when extracting the exception number from the popped xPSR. This correctly strips out the stack alignment bit and restricts the exception number to its valid 9-bit range, matching the behavior in the rest of tlib.

Testing:
Ran a FreeRTOS firmware on an S32K144 simulation. Previously, calling xQueueSendFromISR from within an active CAN interrupt would reliably crash the simulation with Trying to complete not active IRQ HardwareIRQ#512 (528). With this fix, the tail-chaining completes successfully and FreeRTOS context switches perfectly without throwing errors.