fix(arm): enable neon fp16 kernels via march auto-detect and runtime dispatch - #723
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richyreachy wants to merge 12 commits into
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fix(arm): enable neon fp16 kernels via march auto-detect and runtime dispatch#723richyreachy wants to merge 12 commits into
richyreachy wants to merge 12 commits into
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分发链路 请求 kAuto 时按表中行序优先匹配,每行要过两道关——CpuSupports(kernel_arch) 和 HasRequiredCpuFeatures。在 ARM 上:
所以 kAuto 请求下三种度量(SE/Cosine/IP)在任何 ARM 环境都能拿到非空内核,且不会 SIGILL——fp16 指令的翻译单元只有运行时确认 FEAT_FP16 存在才会被选中。显式请求 kNEON 也能成功(命中 NEON-FP16 或普通 NEON 行)。 |
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编译期必须全部满足以下条件,才会定义
任一条件不满足 → 宏关闭,则表行不存在,编译出的二进制里没有 FEAT_FP16 路径。 运行期即使编译进去了,表行还带有
CPU 不支持(如 Cortex-A72 / 树莓派 4,armv8.0)→ 该行被跳过,自动回退到普通 NEON 内核,不会执行非法指令。 典型场景对照
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Problem
The ARM
-marchauto-detect never enables-march=armv8.2-a+fp16, so__ARM_FEATURE_FP16_VECTOR_ARITHMETICis never defined and all native NEON FP16 kernel paths are dead code:_setup_armv8_march()only probed-march=armv8, which GCC rejects outright (cc1: error: bad value 'armv8'); the per-file NEON flag was-march=armv8-a, which does not imply FEAT_FP16 either.Simply bumping the global march flag is not an option: it would emit FP16 instructions unconditionally and SIGILL on ARMv8.0 CPUs (e.g. Graviton1, Cortex-A72 / Raspberry Pi 4). Runtime CPU feature detection is required, mirroring the existing x86 AVX512FP16 setup.
Changes
CMake (
cmake/option.cmake)_setup_armv8_march()to probearmv8-abeforearmv8(GCC compatibility).setup_compiler_march_for_arm(VAR_NEON VAR_NEON_FP16): probesarmv8.2-a+fp16and falls back toarmv8-awhen the compiler cannot target FEAT_FP16.Runtime detection (
ailego/internal/cpu_features)CpuFeatures::FP16()+static_flags_.FP16: readsgetauxval(AT_HWCAP) & HWCAP_ASIMDHPon Linux/aarch64, always true on Apple Silicon, compile-time macro fallback elsewhere.ailego math kernels
*_neonfp16.ccTUs (inner product, squared euclidean, MIPS euclidean), compiled with-march=armv8.2-a+fp16; baseline*_neon.ccTUs keep the cvt-to-fp32 path only.CpuFeatures::static_flags_.FP16at runtime.turbo
distance/neon_fp16/fp16/kernel family (squared euclidean, cosine, inner product + batch variants) using nativevfmaq_f16(8 lanes/op, 4 independent accumulators, widened to FP32 only for the final reduction).kCpuFeatureNeonFp16mask bit wired tostatic_flags_.FP16; registry rows added forkFp16(all three metrics) andkRaw+fp16 ahead