VMMR0/target-x86: hmR0SvmEvaluatePendingEvent fixes - #866
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…lear interrupt-window after injecting NMI. This also fixes the cases where we might try to inject an PIC interrupt after injecting an NMI (would result in a debug assertion). There is a very slight optimization in that if an interrupt is pending while injecting an NMI, we immediately set the interrupt-window pending so we get a VMEXIT earlier rather than evaluating in the next arbitrary VMEXIT opportunity. The overall logic now incidentally also matches the VMX code's counterpart but adapted to AMD-V specifics.
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VMMR0/target-x86: Fix hmR0SvmEvaluatePendingEvent so that we always clear interrupt-window after injecting NMI.
This also fixes the cases where we might try to inject an PIC interrupt after injecting an NMI (would result in a debug assertion).
There is a very slight optimization in that if an interrupt is pending while injecting an NMI, we immediately set the interrupt-window pending so we get a #VMEXIT earlier rather than evaluating in the next arbitrary #VMEXIT opportunity.
The overall logic now incidentally also matches the VMX code's counterpart but adapted to AMD-V specifics.