Suite update - Added designs (Vortex, NVDLA, coralnpu), changed suite update logic

[bgoldbug]

• Changed dev command into update_rtl command. Now, after tracking design updates via update_rtl, the user will be notified that RTL has been updated, and the flow is no longer run after changes are tracked.
  • DEV_FLAG logic was removed from verilog.mk files (and any file generation logic for that matter), and Verilog generation for all designs was incorporated into the setup.sh script. This is NECESSARY, as update_rtl no longer runs the flow, thus verilog.mk won't be triggered by update_rtl.
    • verilog.mk now only holds technology-independent Verilog RTL logic.
    • This should also help any issues using update_rtl.sh for Bazel.
• Added vortex, coralnpu, and NVDLA (small configuration) partitions to the suite (ASAP7).
• Added FakeRAM submodule and corresponding setup logic
• Updated README and added HighTide logo
• Consolidated Markdown documents into a docs folder
• Added a GitHub action that checks if required design files were added