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1. RISC-KC/basic_rv32s RISC-KC/basic_rv32s Public

   🎓 Instructional RISC-V processor design framework: single-cycle to 5-stage pipeline with FPGA verification and complete learning guidelines! A RISC-V CPU design guideline.

   Verilog 70 7

2. RISC-KC/ima_make_rv64 RISC-KC/ima_make_rv64 Public

   I'ma make rv64 cpu.

   Verilog 3

3. RV-IM100 RV-IM100 Public

   RISC-V basic_RV32s / ima_make_RV64 processor architecture based performance analysis repository about Adding Extensions and accelerating operating speed.

   Verilog 2

4. Piveline/smu-piveline Piveline/smu-piveline Public

   FreeRTOS porting on 8-stage pipelined RISC-V CPU with HDMI and keyboards

   Verilog 3