Add doc about SVIF (system verilog interface)

[yportne13]

for this pr: SpinalHDL/SpinalHDL#1364

[andreasWallner]

FYI: while WIP please open as a draft - then it doesn't show up in the inboxes of the maintainers to review.

[Dolu1990]

Hi,

One thing which is important i think, is to specify in the doc that this feature may be subject to changes (experimental)
That will let us more wiggle room for future updates :)

[mrcmry]

Hi !

I have seen that the PR to the spinal lib has been merged in dev and is in v1.14.1.

I did some typo suggestions, you can use the github web interface to add them to a batch and merge them in a commit in the web interface (see this doc).

And then if it's ok for you we can merge this PR.

[mrcmry]

Suggested change

	The ``SVIF`` type specifically targets system Verilog designs.This type extends from ``Bundle``.When generating Verilog or VHDL, the behavior of this type is exactly the same as that of ``Bundle``.However, when generating System Verilog and enabling the ``svInterface`` option in SpinalConfig, this type will be generated as an Interface.
	The ``SVIF`` type specifically targets system Verilog designs. This type extends from ``Bundle``. When generating Verilog or VHDL, the behavior of this type is exactly the same as that of ``Bundle``. However, when generating System Verilog and enabling the ``svInterface`` option in SpinalConfig, this type will be generated as an ``Interface``.

[mrcmry]

Suggested change

	This type is still an experimental feature
	This type is still an experimental feature.

[mrcmry]

Suggested change

	val width = addGeneric("WIDTH", channelWidth)// or addParameter
	val width = addGeneric("WIDTH", channelWidth) // or addParameter

[mrcmry]

Suggested change

	tieGeneric(r, width)// or tieParameter
	tieGeneric(r, width) // or tieParameter

[mrcmry]

Suggested change

	you can use ``setDefinitionName`` to set the definition name. But remember to use it before any clone of this interface
	You can use ``setDefinitionName`` to set the definition name. But remember to use it before any clone of this interface.

[mrcmry]

I'm a bit confuse by "sigA". I can not find it in the spinalhdl code base so I suppose it's some kind of example signal name. Would it not be clearer to call it "mySignal" ?

[mrcmry]

Suggested change

	======
	====

[mrcmry]

Suggested change

	this will generate system verilog code as below:
	This will generate system verilog code as below:

[mrcmry]

Suggested change

	If you have used a certain interface in multiple places, and at one of those locations ``sigA``, you wish to flatten it instead of generating an interface, you can achieve this by calling ``sigA.notSVIF()`` to fully flatten the signal. If the signal has nested interfaces and you only want to expand the outermost layer, you can use ``sigA.notSVIFthisLevel()``.
	If you have used a certain interface in multiple places, and at one of those locations ``mySignal``, you wish to flatten it instead of generating an interface, you can achieve this by calling ``mySignal.notSVIF()`` to fully flatten the signal. If the signal has nested interfaces and you only want to expand the outermost layer, you can use ``mySignal.notSVIFthisLevel()``.