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1 change: 1 addition & 0 deletions configs/nvidia-master.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -1246,6 +1246,7 @@ qwen3.5-fp4-b200-sglang-mtp:
search-space:
- { tp: 4, ep: 1, conc-start: 4, conc-end: 4, spec-decoding: mtp }
- { tp: 2, ep: 1, conc-start: 4, conc-end: 64, spec-decoding: mtp }
- { tp: 2, ep: 2, conc-list: [16, 32, 64], spec-decoding: mtp }

qwen3.5-fp8-b200-sglang-mtp:
image: lmsysorg/sglang:v0.5.14-cu130
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9 changes: 9 additions & 0 deletions perf-changelog.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -5909,3 +5909,12 @@
- "Increase MTP speculative steps from 3 to 5 (num-draft-tokens 4→6) and raise SGLANG_SIMULATE_ACC_LEN from 2.99 to 3.61 to reflect higher measured acceptance rate, targeting ~15% throughput improvement"
- "Replace the TP8/EP8 low-concurrency arm (conc [1,2,4]) hicache offload with kv-offloading: none to reduce per-request latency at low load; conc [1,2,4] are now tested on both tp=4+hicache and tp=8+no-offload so SemiAnalysis can select the Pareto-optimal point per concurrency"
pr-link: https://github.com/SemiAnalysisAI/InferenceX/pull/2570

- config-keys:
- qwen3.5-fp4-b200-sglang-mtp
scenario-type:
- fixed-seq-len
description:
- "Add a TEP2 arm (tp 2, ep 2) to the qwen3.5-fp4-b200-sglang-mtp 8k/1k sweep at concurrency 16, 32, and 64"
- "Rides on the NVFP4-V2 checkpoint switch from #2205"
pr-link: https://github.com/SemiAnalysisAI/InferenceX/pull/2550