Add SQ8↔FP16 ARM SIMD distance kernels [MOD-14972]

[dor-forer]

Describe the changes in the pull request

Add asymmetric SQ8↔FP16 SIMD distance kernels (IP, L2, Cosine) for ARM tiers: NEON_HP, SVE, SVE2. Stacked on PR #970 (MOD-14954), which delivers the x86 equivalents.

The SVE hot loop uses svld1uh_u32 to zero-extend each FP16 halfword into a 32-bit lane, allowing svcvt_f32_f16_x to read the correct bits directly. The NEON residual mirrors the SQ8_FP32 NEON sister: three independent 4-lane sub-steps (r>=4/8/12) leaving at most 3 elements for scalar, replacing the previous single 8-lane block + up-to-7 software conversions.

Which issues this PR fixes

1. MOD-14972

Main objects this PR modified

1. src/VecSim/spaces/IP/IP_NEON_SQ8_FP16.h — new NEON_HP IP kernel
2. src/VecSim/spaces/IP/IP_SVE_SQ8_FP16.h — new SVE/SVE2 IP kernel
3. src/VecSim/spaces/L2/L2_NEON_SQ8_FP16.h — new NEON_HP L2 kernel
4. src/VecSim/spaces/L2/L2_SVE_SQ8_FP16.h — new SVE/SVE2 L2 kernel
5. src/VecSim/spaces/functions/NEON_HP.{h,cpp}, SVE.{h,cpp}, SVE2.{h,cpp} — chooser symbols
6. src/VecSim/spaces/IP_space.cpp, L2_space.cpp — AArch64 dispatcher blocks
7. tests/unit/test_spaces.cpp — tier-walk tests for NEON_HP / SVE / SVE2
8. tests/benchmark/spaces_benchmarks/bm_spaces_sq8_fp16.cpp — ARM microbench registrations

Mark if applicable

• This PR introduces API changes
• This PR introduces serialization changes

---

Note

Medium Risk
Changes hot-path distance math used for vector search; incorrect kernels would skew rankings, though parity tests compare each ARM tier to the scalar baseline within tolerance.

Overview
Adds ARM SIMD paths for asymmetric SQ8 storage ↔ FP16 query inner product, L2², and cosine, complementing the existing x86 SQ8↔FP16 work.

New NEON_HP (asimdhp) kernels process 16-byte SQ8 chunks against FP16 queries widened to FP32, with residual handling aligned to the SQ8↔FP32 NEON pattern. SVE/SVE2 kernels reuse the same math via CHOOSE_SVE_IMPLEMENTATION, loading FP16 with svld1uh_u32 before svcvt_f32_f16. L2 uses the IP core plus precomputed sum-of-squares metadata.

IP_space.cpp / L2_space.cpp (and cosine via IP) now dispatch on AArch64 when dim >= 16, preferring SVE2 → SVE → NEON_HP. Chooser wiring lives in NEON_HP, SVE, and SVE2 function modules. Unit tests tier-walk NEON_HP/SVE/SVE2 against the scalar baseline; benchmarks register the ARM variants when the matching OPT_* build flags and CPU features are present.

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[jit-ci]

🛡️ Jit Security Scan Results

✅ No security findings were detected in this PR

---

^{Security scan by Jit}

[codecov]

Codecov Report

✅ All modified and coverable lines are covered by tests.
✅ Project coverage is 97.11%. Comparing base (daf391f) to head (e1647dc).

Additional details and impacted files

@@            Coverage Diff             @@
##             main     #973      +/-   ##
==========================================
+ Coverage   97.09%   97.11%   +0.02%     
==========================================
  Files         141      141              
  Lines        8110     8110              
==========================================
+ Hits         7874     7876       +2     
+ Misses        236      234       -2     

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[lerman25]

SQ8↔FP16 ARM kernels: proposed optimizations + benchmark results

I profiled the ARM SQ8↔FP16 distance kernels from this PR and prototyped two optimizations, benchmarked head-to-head against this PR's code on a Graviton-4 (Neoverse V2) arm64 runner via bm-spaces.

To keep the comparison clean, both runs are identical except for the kernel changes, and both register spaces_sq8_fp16 in benchmarks.sh (it was built but never emitted by any CI setup, so the kernels had no benchmark coverage):

• Baseline (control): Pr 973 bench baseline #974 — this PR + benchmark registration
• Treatment (proposed opts): Pr 973 bench treatment #975 — baseline + NEON_HP widening + SVE2 FMLALB/FMLALT kernel

Speedup = baseline CPU-time ÷ treatment CPU-time (>1 = faster). 36 dimension points per tier.

Tier	Metric	Median speedup	Range	Median ns (base → treat)
SVE2	L2	1.83×	1.02–1.88	93.6 → 51.0
SVE2	IP	1.84×	1.00–1.89	93.6 → 50.9
SVE2	Cosine	1.84×	1.00–1.89	93.6 → 50.8
NEON_HP	L2	1.05×	1.02–1.15	103.0 → 97.7
NEON_HP	IP	1.05×	1.02–1.09	103.0 → 97.8
NEON_HP	Cosine	1.05×	1.02–1.10	103.0 → 97.7
SVE (untouched control)	all	1.00×	1.00–1.01	unchanged

What changed

• SVE2 (~1.83–1.84×, near the theoretical 2×): a dedicated kernel using the FMLALB/FMLALT widening multiply-accumulate pair (svmlalb_f32/svmlalt_f32), keeping storage+query at 16 bits and processing svcnth lanes/step vs the base svcntw — doubling throughput and removing explicit query widening. By bucket: high_dim 1.86×, residual 1.85×, low_dim 1.55–1.58× (per-call overhead dilutes small dims), 512-bit chunks median 1.66× with min ~1.00× at Dimension:16 (single chunk → nothing to amortize, no regression).
• NEON_HP (steady ~1.05×): widen SQ8 storage uint8 → fp16 → fp32 via vcvtq_f16_u16 (values 0..255 are exact in FP16), dropping two integer-widening ops per 16-element chunk with identical FP32 lane values.

Why this is trustworthy

The untouched base SVE tier reads 1.00×, confirming the comparison is clean (identical code → identical perf) — so the gains are attributable to the kernels, not run-to-run noise. No regressions anywhere (min speedup ≥ 1.00 in every tier).

Happy to fold these into this PR if you'd like — the diffs are small and isolated to the IP/L2 SVE2 headers + the NEON_HP step + the SVE2 chooser.