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Reorganize#2

Merged

rodrigomelo9 merged 14 commits intomainPyFPGA/HDLtools:mainfrom

reorganizePyFPGA/HDLtools:reorganizeCopy head branch name to clipboard

Dec 30, 2025

Conversation Commits14 (14)Checks Files changed

Merged

Reorganize#2
rodrigomelo9 merged 14 commits intomainfrom
reorganize

Commits

Commits on Mar 29, 2025

Remove HdlDetect
rodrigomelo9
committed
Rewritten GenFile as HDLWriter
rodrigomelo9
committed
Rewritten HdlSanitize as HDLReader
rodrigomelo9
committed
Rename mod_parse as mod_parser, and applied small changes
rodrigomelo9
committed

Commits on Mar 30, 2025

Add Function cli_parser
rodrigomelo9
committed
Re-implemented apps after last changes
rodrigomelo9
committed

Commits on Apr 4, 2025

Fix pylint complaints
rodrigomelo9
committed
Add method to detect if code is VHDL or not
rodrigomelo9
committed

Commits on Apr 6, 2025

Add Class HDLController
rodrigomelo9
committed
Fix the wrong accumulation of parsed results
rodrigomelo9
committed
apps: simplified employing HDLController
rodrigomelo9
committed
Move logic from genwrap and genstub to hdl_controller
rodrigomelo9
committed

Commits on Apr 7, 2025

Tests renamed and updated
rodrigomelo9
committed
Simplified tests using fixtures
rodrigomelo9
committed

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