[dv] Add boundary-condition regression for timer and PWM

[briann-bui]

Problem

The timer UVM environment currently has one smoke sequence. It needs self-checking boundary tests for the timer, PWM, one-shot behavior, and interrupt status handling.

Scope

Extend verification without changing the public register map. Prefer small tests and reusable reference-model logic over one large sequence.

Scenarios to cover

• Prescaler values 0, 1, and 16'hFFFF.
• Reload values 0, 1, and a representative normal period.
• Compare values below, equal to, and above reload.
• PWM duty-cycle boundaries, including effectively 0% and 100% behavior as defined by the current RTL.
• Continuous reload and one-shot stop behavior.
• Direct writes to VALUE while disabled and enabled.
• Overflow and compare IRQ enable, masking, simultaneous events, and write-one-to-clear status.
• Reset while disabled and during an active count.

Deliverables

• A cycle-accurate reference model or equivalent self-checking scoreboard.
• Focused UVM sequences/tests for the scenarios above.
• Assertions for key invariants such as disabled counter stability, one-shot completion, and PWM low when disabled.
• Functional coverage for mode, prescaler class, compare/reload relation, IRQ source, and clear behavior.

Acceptance criteria

• Every scenario is self-checking; log-only observation is not sufficient.
• Tests do not rely on fragile fixed delays where clock/event synchronization is possible.
• Existing smoke test continues to pass.
• make lint, make compile, and the complete timer regression pass.
• README lists the added tests and exact run commands.

This task can be split: a first-time contributor may claim one focused scenario or assertion set. Please comment with the part you want to implement and follow the contribution rules.

[briann-bui]

Hi @Raghavan-04 — welcome, and thanks for volunteering! Your proposed SVA-focused scope is a good fit for a first contribution. I’m reserving the Timer/PWM assertions and invariant checks portion of this issue for you.

For the first PR, please focus on:

• counter stability while disabled and defined behavior for direct writes to VALUE;
• one-shot completion and stop behavior;
• PWM output in disabled/forced-low states and at boundary duty cycles;
• irq matching the enabled, unmasked status sources.

Please keep the PR limited to assertions plus any minimal assertion-directed tests needed to demonstrate pass/fail behavior. Avoid public register-map or functional RTL changes. Include the exact lint/simulation commands and results in the PR description, and link the PR with Refs #1.

The broader scoreboard, UVM regression, and functional coverage can remain for follow-up contributions after this focused set is reviewed. Feel free to ask here if any RTL behavior is ambiguous before encoding it as an assertion.